Abstract: Techniques are described for systematically and efficiently converting or otherwise accelerating latent defects in semiconductor devices into gross defects by applying appropriate defect acceleration stimulus to the semiconductor devices. Techniques are also described for evaluating test patterns to determine their effectiveness in accelerating the transition of latent defects to gross defects. This evaluation effectively allows various stress patterns to be graded or ranked, so that an optimal or high-confidence one can be selected. Such grading of possible stress patterns increases the probability that a given latent defect will escalate or otherwise manifest.

Abstract: Techniques are described for systematically and efficiently converting or otherwise accelerating latent defects in semiconductor devices into gross defects by applying appropriate defect acceleration stimulus to the semiconductor devices. Techniques are also described for evaluating test patterns to determine their effectiveness in accelerating the transition of latent defects to gross defects. This evaluation effectively allows various stress patterns to be graded or ranked, so that an optimal or high-confidence one can be selected. Such grading of possible stress patterns increases the probability that a given latent defect will escalate or otherwise manifest.