Patents by Inventor Surjit S. Chadha

Surjit S. Chadha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5688438
    Abstract: A method of preparing a silicate-containing phosphor is provided. The method includes combining a mixture of metal or metalloid compounds with a gaseous silicon-containing in an amount sufficient to convert the compounds to silicates, and heating the silicates under conditions effective to form a phosphor.
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: November 18, 1997
    Assignee: Micron Display Technology, Inc.
    Inventor: Surjit S. Chadha
  • Patent number: 5668437
    Abstract: A conductive, light-absorbing baseplate for use in a field emission display is disclosed. The interior surface of the baseplate is coated with a praseodymium-manganese oxide layer having a resistivity that does not exceed 1.times.10.sup.5 .OMEGA..multidot.cm. A field emission display is also disclosed which comprises the conductive, light-absorbing baseplate, as well as processes for manufacturing the baseplate, field emission display and the conductive, light-absorbing praseodymium-manganese oxide material used to coat the baseplate.
    Type: Grant
    Filed: May 14, 1996
    Date of Patent: September 16, 1997
    Assignee: Micro Display Technology, Inc.
    Inventors: Surjit S. Chadha, Robert T. Rasmussen
  • Patent number: 5662831
    Abstract: There is disclosed a luminescent phosphor having an average particle size of less than about 3 microns, as well as a bright luminescent phosphor having an average particle size of less than 5 microns and a luminescence of about 10-12 au. The bright luminescent phosphor is made by combing a yttrium or gadolinium host material with a europium dopant in a liquid to form a slurry, and then pulverizing the slurry to less than about 3 microns in average particle size. The pulverized slurry is then heated to yield the bright luminescent phosphor. The bright luminescent phosphor is particularly suited for use in high resolution display screens, and in screens which require low power consumption, such as laptop computers.
    Type: Grant
    Filed: May 31, 1996
    Date of Patent: September 2, 1997
    Assignee: Micron Display Technology, Inc.
    Inventor: Surjit S. Chadha
  • Patent number: 5641416
    Abstract: A process for separating FED baseplates or other types of die assemblies from one another without producing any particulate matter or slag that could damage some of the baseplates. In one embodiment a high energy beam is aligned with a cutting line on the wafer that defines a path between the die assemblies along which the wafer is to be cut. At least one of the high energy beam or the wafer is moved in the direction of the cutting line so that the high energy beam passes over the wafer and penetrates the wafer to an intermediate depth along the length of the cutting line. The moving step is then repeated after each pass of the high energy beam over the wafer until the wafer is severed along the cutting path.
    Type: Grant
    Filed: October 25, 1995
    Date of Patent: June 24, 1997
    Assignee: Micron Display Technology, Inc.
    Inventor: Surjit S. Chadha
  • Patent number: 5635110
    Abstract: A multi-stage process for preparing a phosphor product includes the stages of selecting precursors of a dopant and a host lattice as the phosphor starting materials, grinding the starting materials in an initial grinding stage for an initial grinding time period to produce an initial ground material having a smaller particle size distribution than the starting materials, firing the initial ground material in an initial firing stage at an initial firing temperature for an initial firing time period to produce an initial fired material, grinding the initial fired material in an intermediate grinding stage for an intermediate grinding time period to produce an intermediate ground material having a smaller particle size than the initial fired material, wherein the intermediate grinding time period is substantially less than the initial grinding time period, firing the intermediate ground material in an intermediate firing stage at an intermediate firing temperature for an intermediate firing time to produce an in
    Type: Grant
    Filed: October 25, 1995
    Date of Patent: June 3, 1997
    Assignee: Micron Display Technology, Inc.
    Inventors: Surjit S. Chadha, Charles M. Watkins
  • Patent number: 5601751
    Abstract: A process is provided for manufacturing high-purity phosphors having utility in field emission displays. The high-purity phosphor is a host lattice infiltrated by a dopant that activates luminescent properties therein. The lattice and dopant are initially milled together to reduce their average particle size while simultaneously achieving complete mixing between the lattice and the dopant. The resulting mixture is maintained free of a flux or substantially any other treatment agent capable of contaminating the phosphor and placed in a heating vessel formed from a substantially impervious contaminant-free material. The mixture is heated to a high temperature effectuating thorough infiltration of the dopant into the lattice structure. The use of an impervious contaminant-free heating vessel and the exclusion of flux or other treatment agents from the mixture avoids undesirable contamination and undue particle size growth of the phosphor product during the manufacture thereof.
    Type: Grant
    Filed: June 8, 1995
    Date of Patent: February 11, 1997
    Assignee: Micron Display Technology, Inc.
    Inventors: Charles M. Watkins, Surjit S. Chadha
  • Patent number: 4529885
    Abstract: A direct current electroluminescent device having a phosphor layer and coating electrodes, at least one of which is translucent, which has interposed between the phosphor layer and at least one of said electrodes a thin non-planar layer of an electrically non-conducting substance. The non-planar layer may have a cross section of undulating outline or may be a discontinuous layer, e.g. in the form of closely spaced dots. Preferably the non-planar layer is translucent and is arranged between the phosphor layer and a translucent electrode. Suitable materials for the non-planar layer include silicon monoxide, silicon dioxide, germanium dioxide, magnesium fluoride, cadmium fluoride, yttrium fluoride, yttrium oxide, zinc sulphide, copper sulphide.
    Type: Grant
    Filed: December 1, 1982
    Date of Patent: July 16, 1985
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Michael S. Waite, Surjit S. Chadha, Weng Y. Leong