Abstract: A microcontroller includes a plurality of (Intellectual Property) IP blocks each configured to perform one or more functions; a hardware power estimator circuit for estimating power of the microcontroller, the hardware power estimator including a hardware artificial neural network inlcuding a plurality of interconnected nodes arranged in one or more stages, wherein each individual stage comprises: a first input layer including values indicating activities of the microcontroller and/or indicating active cells of the microcontroller; a second input layer including a weighted set of values; an output layer including values calculated for the individual node stage; and at least one intermediate layer situated between the input layer and the output layer, wherein each node of the at least one intermediate layer comprises a multiply and adder (MADD) circuit that is configured to calculate a value for the respective node using values received from the first and second input layers.

Abstract: A microcontroller powered by a power management integrated circuit (PMIC) includes a plurality of cores. A first core of the microcontroller can be configured to implement a system power transient management component. One or more other or second cores of the microcontroller can be configured to implement one or more applications. The system power transient management component implemented by the first core can be configured to dynamically identify an expected load transient event to occur in the microcontroller, determine power control data to optimize a response to the identified expected load transient event, the power control data comprising a power control mode and associated parameters, and provide the power control data to the power management integrated circuit (PMIC).

Abstract: A microcontroller powered by a power management integrated circuit (PMIC) includes a plurality of cores. A first core of the microcontroller can be configured to implement a system power transient management component. One or more other or second cores of the microcontroller can be configured to implement one or more applications. The system power transient management component implemented by the first core can be configured to dynamically identify an expected load transient event to occur in the microcontroller, determine power control data to optimize a response to the identified expected load transient event, the power control data comprising a power control mode and associated parameters, and provide the power control data to the power management integrated circuit (PMIC).

Abstract: A arrangement is disclosed for an on-chip system having an increased resolution for supply voltage measurements. The system includes a phase locked loop (PLL), a divider, and a timer. The PLL is configured to generate an oscillator signal. The divider is configured to divide the oscillator signal to generate an divided clock signal. The timer is configured to generate an application start signal and an analog to digital converter (ADC) start signal based on the oscillator signal and a timer delay (Tdelay). The timer delay (Tdelay) is based on the application start signal and the ADC start signal.

Abstract: A arrangement is disclosed for an on-chip system having an increased resolution for supply voltage measurements. The system includes a phase locked loop (PLL), a divider, and a timer. The PLL is configured to generate an oscillator signal. The divider is configured to divide the oscillator signal to generate an divided clock signal. The timer is configured to generate an application start signal and an analog to digital converter (ADC) start signal based on the oscillator signal and a timer delay (Tdelay). The timer delay (Tdelay) is based on the application start signal and the ADC start signal.