Patents by Inventor Surya Musunuri
Surya Musunuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11095119Abstract: A voltage of a first pin that is one of several pins of an external connector of a system is measured, while the first pin is un-driven except for being pulled to ground through a first resistance, and a second pin of the external connector is being used as a power supply rail of the system. The measured voltage is compared to a short circuit threshold and in response to that threshold being exceeded, the power supply voltage on the second pin is reduced. In such an embodiment, no test stimulus needs to be applied to any of the pins of the external connector. Other embodiments are also described and claimed.Type: GrantFiled: January 28, 2019Date of Patent: August 17, 2021Assignee: Apple Inc.Inventors: Roderick D. Bacon, Nagendra Bage Jayaraj, Derek J. DiCarlo, Chi Kin Ho, Xingqun Li, Jahan C. Minoo, Surya Musunuri, Tony Chi Wang Ng, Carlos Ribas, Ching Yu John Tam, Evan J. Thompson, Daniel C. Wagman, Di Zhao, Robert D. Zupke
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Patent number: 10712768Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.Type: GrantFiled: January 18, 2019Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Surya Musunuri, Jagannadha R. Rapeta, Mark L. Elzinga, Young Min Park, Robert R. Fulton
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Publication number: 20190220054Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.Type: ApplicationFiled: January 18, 2019Publication date: July 18, 2019Applicant: Intel CorporationInventors: Surya Musunuri, Jagannadha R. Rapeta, Mark L. Elzinga, Young Min Park, Robert R. Fulton
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Publication number: 20190173276Abstract: A voltage of a first pin that is one of several pins of an external connector of a system is measured, while the first pin is un-driven except for being pulled to ground through a first resistance, and a second pin of the external connector is being used as a power supply rail of the system. The measured voltage is compared to a short circuit threshold and in response to that threshold being exceeded, the power supply voltage on the second pin is reduced. In such an embodiment, no test stimulus needs to be applied to any of the pins of the external connector. Other embodiments are also described and claimed.Type: ApplicationFiled: January 28, 2019Publication date: June 6, 2019Applicant: Apple Inc.Inventors: Roderick D. Bacon, Nagendra Bage Jayaraj, Derek J. DiCarlo, Chi Kin Ho, Xingqun Li, Jahan C. Minoo, Surya Musunuri, Tony Chi Wang Ng, Carlos Ribas, Ching Yu John Tam, Evan J. Thompson, Daniel C. Wagman, Di Zhao, Robert D. Zupke
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Patent number: 10236683Abstract: A voltage of a first pin that is one of several pins of an external connector of a system is measured, while the first pin is un-driven except for being pulled to ground through a first resistance, and a second pin of the external connector is being used as a power supply rail of the system. The measured voltage is compared to a short circuit threshold and in response to that threshold being exceeded, the power supply voltage on the second pin is reduced. In such an embodiment, no test stimulus needs to be applied to any of the pins of the external connector. Other embodiments are also described and claimed.Type: GrantFiled: September 2, 2016Date of Patent: March 19, 2019Assignee: Apple Inc.Inventors: Roderick D. Bacon, Nagendra Bage Jayaraj, Derek J. DiCarlo, Chi Kin Ho, Xingqun Li, Jahan C. Minoo, Surya Musunuri, Tony Chi Wang Ng, Carlos Ribas, Ching Yu John Tam, Evan J. Thompson, Daniel C. Wagman, Di Zhao, Robert D. Zupke
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Patent number: 10185349Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.Type: GrantFiled: December 3, 2013Date of Patent: January 22, 2019Assignee: Intel CorporationInventors: Surya Musunuri, Jagannadha R. Rapeta, Mark L. Elzinga, Young Min Park, Robert Fulton
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Publication number: 20170358922Abstract: A voltage of a first pin that is one of several pins of an external connector of a system is measured, while the first pin is un-driven except for being pulled to ground through a first resistance, and a second pin of the external connector is being used as a power supply rail of the system. The measured voltage is compared to a short circuit threshold and in response to that threshold being exceeded, the power supply voltage on the second pin is reduced. In such an embodiment, no test stimulus needs to be applied to any of the pins of the external connector. Other embodiments are also described and claimed.Type: ApplicationFiled: September 2, 2016Publication date: December 14, 2017Inventors: Roderick D. Bacon, Nagendra Bage Jayaraj, Derek J. DiCarlo, Chi Kin Ho, Xingqun Li, Jahan C. Minoo, Surya Musunuri, Tony Chi Wang Ng, Carlos Ribas, Ching Yu John Tam, Evan J. Thompson, Daniel C. Wagman, Di Zhao, Robert D. Zupke
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Patent number: 9628094Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.Type: GrantFiled: September 26, 2013Date of Patent: April 18, 2017Assignee: Intel CorporationInventors: Amr M. Lotfy, Mohamed A. Abdelsalam, Mamdouh O. Abd El-Mejeed, Nasser A. Kurd, Mohamed A. Abdelmoneum, Mark Elzinga, Young Min Park, Jagannadha R. Rapeta, Surya Musunuri
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Publication number: 20160266603Abstract: Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having a feedback divider, the locked loop to receive a reference clock and to compare it with a feedback clock which is output from the feedback divider, and to generate an output clock; a post locked loop divider, coupled to the locked loop, to receive the output clock and to generate a base clock for other logic units; and a control logic to adjust first and second divider ratios for the feedback divider and the post locked loop divider respectively for over-clocking or under-clocking the base clock such that the locked loop remains locked while being over-clocked or under-clocked.Type: ApplicationFiled: December 3, 2013Publication date: September 15, 2016Inventors: Surya MUSUNURI, Jagannadha R. RAPETA, L. Mark ELZINGA, Young Min PARK, Robert FULTON
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Publication number: 20160204787Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.Type: ApplicationFiled: September 26, 2013Publication date: July 14, 2016Inventors: Amr M. LOTFY, Mohamed A. ABDELSALAM, Mamdouh O. ABD EL-MEJEED, Nasser A. KURD, Mohamed A. ABDELMONEUM, Mark ELZINGA, Young Min PARK, Jagannadha R. RAPETA, Surya MUSUNURI
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Patent number: 7808283Abstract: An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.Type: GrantFiled: September 25, 2008Date of Patent: October 5, 2010Assignee: Intel CorporationInventors: Praveen Dani, Robert Fulton, Andrew M. Volk, Surya Musunuri
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Publication number: 20100073035Abstract: An apparatus for clock generation is presented. In one embodiment, the apparatus comprises a phase interpolator that generates an output with a phase value within reference phases associated with two input clocks. Logic units are coupled to determine a number of phase settings for the phase interpolator. A divider is coupled to the phase interpolator to generate an output clock based on a modifiable divider setting.Type: ApplicationFiled: September 25, 2008Publication date: March 25, 2010Inventors: Praveen Dani, Robert Fulton, Andrew M. Volk, Surya Musunuri