Abstract: A multiple-phase parallelable constant on time (COT) buck controller, a first phase containing a first memory bit and a second phase containing a second memory bit. The COT buck controller includes a first converter comprising a first constant TON generator configured to sense and deliver a first TON request when the first memory bit is in a logic one state, and a second converter connected in parallel with the first converter, the second converter comprising a second constant TON generator configured to sense and deliver a second TON request when the second memory bit is in the logic one state, only one of the first memory bit and the second memory bit being in the logic one state thus generating activity in a daisy chain ring where each of the first converter and the second converter senses and delivers a corresponding TON request in a sequential manner.

Abstract: A multiple-phase parallelable constant on time (COT) buck controller, a first phase containing a first memory bit and a second phase containing a second memory bit. The COT buck controller includes a first converter comprising a first constant TON generator configured to sense and deliver a first TON request when the first memory bit is in a logic one state, and a second converter connected in parallel with the first converter, the second converter comprising a second constant TON generator configured to sense and deliver a second TON request when the second memory bit is in the logic one state, only one of the first memory bit and the second memory bit being in the logic one state thus generating activity in a daisy chain ring where each of the first converter and the second converter senses and delivers a corresponding TON request in a sequential manner.

Abstract: A multi-phase DC-to-DC buck converter for receiving an input voltage and delivering an output voltage to a load by splitting the load current between a plurality of DC-to-DC buck converter cells. The converter includes a plurality of current sense circuits for sensing current in a respective converter cell, each of the current sense circuits configured to generate a respective current sense signal, an averaging circuit for receiving each of the respective current sense signals and generating an average signal, a plurality of imbalance detector circuits for comparing a respective current sense signal with the average signal and generating a respective current imbalance signal, and a plurality of ON time generators for activating a converter cell for a predetermined time interval and altering the predetermined time interval in accordance with a time integral of a respective current imbalance signal.