Patents by Inventor Surya Theja GOLAKONDA

Surya Theja GOLAKONDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11323109
    Abstract: A clockless delay adaptation loop configured to adapt to random data includes a first and a second delay line, an autocorrelator, and a controller. The autocorrelator receives an input signal for the delay adaptation loop and the output from the first delay line, and includes a first logic circuit configured to output a first autocorrelation and a second logic circuit configured to output a second autocorrelation. The controller is configured generate a control signal for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate, and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is two times a gain of the XNOR gate. In some examples, an amplifier having two times the gain of the XNOR gate is coupled to the OR gate.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abishek Manian, Surya Theja Golakonda, Robin Gupta
  • Publication number: 20210409014
    Abstract: A clockless delay adaptation loop configured to adapt to random data includes a first and a second delay line, an autocorrelator, and a controller. The autocorrelator receives an input signal for the delay adaptation loop and the output from the first delay line, and includes a first logic circuit configured to output a first autocorrelation and a second logic circuit configured to output a second autocorrelation. The controller is configured generate a control signal for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate, and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is two times a gain of the XNOR gate. In some examples, an amplifier having two times the gain of the XNOR gate is coupled to the OR gate.
    Type: Application
    Filed: October 30, 2020
    Publication date: December 30, 2021
    Inventors: Abishek MANIAN, Surya Theja GOLAKONDA, Robin GUPTA