Patents by Inventor Suryanarayan G. Hegde
Suryanarayan G. Hegde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7453123Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.Type: GrantFiled: February 16, 2007Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanarayan G. Hegde, Meikei Ieong, Erin Catherine Jones
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Publication number: 20080246090Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.Type: ApplicationFiled: May 13, 2008Publication date: October 9, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanarayan G. Hegde, MeiKei Ieong, Erin Catherine Jones
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Patent number: 7205185Abstract: A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.Type: GrantFiled: September 15, 2003Date of Patent: April 17, 2007Assignee: International Busniess Machines CorporationInventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanarayan G. Hegde, MeiKei Ieong, Erin Catherine Jones
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Patent number: 6878978Abstract: The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETS, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.Type: GrantFiled: June 29, 2004Date of Patent: April 12, 2005Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Dureseti Chidambarrao, Suryanarayan G. Hegde
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Patent number: 6858488Abstract: The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains if the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.Type: GrantFiled: June 29, 2004Date of Patent: February 22, 2005Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Dureseti Chidambarrao, Suryanarayan G. Hegde
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Patent number: 6833569Abstract: The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.Type: GrantFiled: December 23, 2002Date of Patent: December 21, 2004Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Bruce B. Doris, Suryanarayan G. Hegde, Meikei Ieong, Erin C. Jones
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Patent number: 6803270Abstract: The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.Type: GrantFiled: February 21, 2003Date of Patent: October 12, 2004Assignee: International Business Machines CorporationInventors: Omer H. Dokumachi, Dureseti Chidambarrao, Suryanarayan G. Hegde
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Publication number: 20040166624Abstract: The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.Type: ApplicationFiled: February 21, 2003Publication date: August 26, 2004Applicant: International Business Machines CorporationInventors: Omer H. Dokumaci, Dureseti Chidambarrao, Suryanarayan G. Hegde
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Publication number: 20040121549Abstract: The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Inventors: Omer H. Dokumaci, Bruce B. Doris, Suryanarayan G. Hegde, Meikei Ieong, Erin C. Jones
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Publication number: 20040082197Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.Type: ApplicationFiled: October 29, 2002Publication date: April 29, 2004Applicants: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Oleg Gluschenkov, Suryanarayan G. Hegde, Helmut H. Tews
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Patent number: 6727142Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.Type: GrantFiled: October 29, 2002Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Oleg Gluschenkov, Suryanarayan G. Hegde, Helmut H. Tews
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Publication number: 20040051162Abstract: As disclosed herein, a structure and method is provided for forming an integrated circuit including a reduced programming voltage antifuse on a semiconductor substrate. The method includes doping a portion of a semiconductor substrate with nitrogen and a charge carrier dopant source, and forming a thin dielectric over the doped portion of the semiconductor substrate, wherein the thin dielectric is subject to breakdown upon application of a breakdown voltage. The method further includes forming a first conductor separated from the semiconductor substrate by the thin dielectric, and forming a second conductor conductively coupled to the doped portion of the semiconductor substrate.Type: ApplicationFiled: September 13, 2002Publication date: March 18, 2004Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Infineon Technologies North America Corp.Inventors: Dureseti Chidambarrao, Ulrich Frey, Suryanarayan G. Hegde, William Robert Tonti
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Patent number: 6569781Abstract: A method for forming an oxide layer on a silicon substrate includes forming a sacrificial oxide layer on the silicon substrate, implanting nitrogen into the silicon substrate, annealing the silicon substrate having implanted nitrogen, removing the sacrificial oxide layer from the silicon substrate, and forming an oxide layer on the silicon substrate. The dose of nitrogen implanted into silicon is preferably higher than 1e14 cm31 2. The annealing process is preferably performed at temperatures in a range from about 550° C. to about 1000° C. and for a time period between about 1 second and about 2 hours.Type: GrantFiled: January 22, 2002Date of Patent: May 27, 2003Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Richard D. Kaplan, Mukesh V. Khare, Suryanarayan G. Hegde
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Patent number: 6514843Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, Cl, He, Ar, Kr, and Xe; and mixtures thereof.Type: GrantFiled: April 27, 2001Date of Patent: February 4, 2003Assignee: International Business Machines CorporationInventors: Omer Dokumaci, Oleg Gluschenkov, Suryanarayan G. Hegde, Richard Kaplan, Mukesh Khare
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Publication number: 20020197836Abstract: A method for forming variable oxide thicknesses across semiconductor chips comprises providing a silicon semiconductor substrate having pre-selected areas open to silicon surface using a photoresist layer; immersing the silicon semiconductor substrate in an HF type electrolytic bath to produce a porous silicon area; and removing the photoresist layer and oxidizing the silicon semiconductor substrate to produce a plurality of thicknesses of gate oxide on the silicon semiconductor substrate.Type: ApplicationFiled: June 11, 2001Publication date: December 26, 2002Applicant: International Business Machines CorporationInventors: S. Sundar Kumar Iyer, Suryanarayan G. Hegde, Erin Catherine Jones, Harald F. Okorn-Schmidt
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Publication number: 20020160593Abstract: A method of enhancing the rate of transistor gate corner oxidation, without significantly increasing the thermal budget of the overall processing scheme is provided. Specifically, the method of the present invention includes implanting ions into gate corners of a Si-containing transistor, and exposing the transistor including implanted transistor gate corners to an oxidizing ambient. The ions employed in the implant step include Si; non-retarding oxidation ions such as O, Ge, As, B, P, In, Sb, Ga, F, Cl, He, Ar, Kr, and Xe; and mixtures thereof.Type: ApplicationFiled: April 27, 2001Publication date: October 31, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Omer Dokumaci, Oleg Gluschenkov, Suryanarayan G. Hegde, Richard Kaplan, Mukesh Khare
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Patent number: 6387782Abstract: A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate.Type: GrantFiled: June 6, 2001Date of Patent: May 14, 2002Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Hiroyuki Akatsu, Omer H. Dokumaci, Suryanarayan G. Hegde, Yujun Li, Rajesh Rengarajan, Paul A. Ronsheim
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Patent number: 6348388Abstract: A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a <100> crystal plane and a <110> crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the <110> crystal plane of the trench side wall, but not into the <100> crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.Type: GrantFiled: September 20, 2000Date of Patent: February 19, 2002Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Johnathan E. Faltermeier, Ulrike Gruening, Suryanarayan G. Hegde, Rajarao Jammy, Brian S. Lee, Helmut H. Tews
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Patent number: 6329704Abstract: A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate.Type: GrantFiled: December 9, 1999Date of Patent: December 11, 2001Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Hiroyuki Akatsu, Omer H. Dokumaci, Suryanarayan G. Hegde, Yujun Li, Rajesh Rengarajan, Paul A. Ronsheim
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Publication number: 20010030333Abstract: A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate.Type: ApplicationFiled: June 6, 2001Publication date: October 18, 2001Inventors: Hiroyuki Akatsu, Omer H. Dokumaci, Suryanarayan G. Hegde, Yujun Li, Rajesh Rengarajan, Paul A. Ronsheim