Patents by Inventor Suryanarayana Duggirala

Suryanarayana Duggirala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7900105
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: March 1, 2011
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7836367
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: November 16, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7836368
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: November 16, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20100223516
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: May 12, 2010
    Publication date: September 2, 2010
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7774663
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: August 10, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7743299
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: June 22, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20100031101
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: August 11, 2009
    Publication date: February 4, 2010
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20090313514
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: August 24, 2009
    Publication date: December 17, 2009
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20090271673
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: July 9, 2009
    Publication date: October 29, 2009
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7596733
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: September 29, 2009
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20080301510
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: July 23, 2008
    Publication date: December 4, 2008
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20080294955
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: July 23, 2008
    Publication date: November 27, 2008
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7418640
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: August 26, 2008
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20050268190
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 1, 2005
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas Williams
  • Patent number: 6766501
    Abstract: A process and system for placement planning for test mode circuitry of an integrated circuit design. The novel method includes the steps of partitioning a scan chain of a netlist into sets of re-orderable scan cells. The netlist is passed to layout processes and therein the scan cells of the scan chain are re-ordered based on the sets. According to one embodiment of the present invention, the scan-chain is partitioned into a number of different sets based the respective clock domains, edge sensitivity types, skew tolerance levels, surrounding cone logic, reconfigurability and simultaneous output switching requirements of the scan cells. Data representative of the resulting sets are then provided to the place-and-route processes to be used as re-ordering limitations. Particularly, the re-ordering limitations restrict the rearrangement of scan cells among different sets. The placement and routing processes, however, are not restricted from rearranging the order of scan cells within the same set.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: July 20, 2004
    Assignee: Synopsys, Inc.
    Inventors: Suryanarayana Duggirala, Rohit Kapur, Thomas W. Williams
  • Patent number: 6434733
    Abstract: A process and system for placement planning for test mode circuitry of an integrated circuit design. The novel method includes the steps of partitioning a scan chain of a netlist into sets of re-orderable scan cells. The netlist is passed to layout processes and therein the scan cells of the scan chain are re-ordered based on the sets. According to one embodiment of the present invention, the scan-chain is partitioned into a number of different sets based the respective clock domains, edge sensitivity types skew tolerance levels, surrounding cone logic, reconfigurability and simultaneous output switching requirements of the scan cells. Data representative of the resulting sets are then provided to the place-and-route processes to be used as re-ordering limitations. Particularly, the re-ordering limitations restrict the rearrangement of scan cells among different sets. The placement and routing processes, however, are not restricted from rearranging the order of scan cells within the same set.
    Type: Grant
    Filed: March 24, 1999
    Date of Patent: August 13, 2002
    Assignee: Synopsys, Inc.
    Inventors: Suryanarayana Duggirala, Rohit Kapur, Thomas W. Williams
  • Patent number: 6405355
    Abstract: A computer implemented method of constructing a scan chain. According to the present invention, scan cells are inserted into a netlist description of an integrated circuit design and are coupled serially together to form a scan chain. The resulting netlist is then passed to layout processes where the cells of the integrated circuit design are automatically placed and routed. The layout processes are performed without regard to any predetermined constraints designating any particular functional pins of the netlist design as scan-in or scan-out ports for the scan chain. After the cells are placed, a first functional pin is selected as the scan-in port and a second functional pin is selected as the scan-out port according to cell placement information. In particular, the functional pin that is closest to the leading scan cell is selected as the scan-in port. The functional pin that is closest to the last scan cell is selected as the scan-out port for the scan chain.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: June 11, 2002
    Assignee: Synopsys, Inc.
    Inventors: Suryanarayana Duggirala, Rohit Kapur, Thomas W. Williams
  • Patent number: 6269463
    Abstract: A method and system for generating test vectors for testing scan-based sequential circuits that contain non-scan cells using combinational ATPG techniques. The present invention includes the computer implemented step of receiving a netlist description of an integrated circuit device that comprises scan cells and non-scannable cells. Under certain conditions, some non-scan cells may exhibit sequential transparency behavior. The present invention identifies such conditions and characterizes each non-scan cell as sequentially transparent or non-transparent. Based on such characterization, the present invention transforms non-scan cells exhibiting sequential transparency behavior with transparent logic models during combinational ATPG (Automatic Test Pattern Generation) analysis. Because non-scan cells of exhibiting sequential transparency behavior are not replaced with “force-to-X” models, the fault coverage of the test patterns thus generated is significantly improved.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: July 31, 2001
    Assignee: Synopsys, Inc.
    Inventors: Suryanarayana Duggirala, Harihara Ganesan, Cyrus Hay