Abstract: Built-In Self Test (BIST) is a test technique wherein semiconductor integrated circuit devices test themselves during their operation lifetime. BIST techniques do not necessarily require additional hardware; they can be implemented using dedicated software routines. Various BIST algorithms and techniques have been proposed for testing random access memory (RAM) devices. The present invention provides an architecture for the memory-test interface that allows the serial transfer of the test background data from the BIST controller to the interface of the memory-under-test using a single bit with serial-to-parallel data conversion using a shift register in the memory interface. The size of the shift register is equal to the word width of the memory-under-test.

Abstract: An exemplary CAD design flow modifies an existing large scale chip layout to reinforce the redundant via design rules to improve the yield and reliability. The flow operates on each metal-via pair from bottom up to locate and correct isolated via rule violations by adding metal features and vias in a respective patch cell associated with each cluster cell. A large complex design is thus divided into cells so that multiple processes can work concurrently as if every process were working on the top level of the design layout.