Abstract: A circuit and method for providing a current limiting feature in a low dropout (“LDO”) linear voltage regulator. A pass element generates an output voltage that is less than the input voltage. The pass element is normally enabled by an error amplifier that compares a feedback signal from the output of the pass element with a reference signal. However, the pass element may be enabled by a current limiting circuit that bypasses the error amplifier to limit the current generated at the output of the pass element.

Abstract: An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta analog to digital converter configured for direct connection to an analog output of a touch screen device, and further including an integrator circuit having an input coupled for receiving the analog output signal and outputting an integrated output voltage; a comparator coupled to the integrated output voltage and a first bias voltage and outputting a comparison voltage; a clocked sampling latch coupled to the comparison voltage and to a clock signal and outputting quantized data bits corresponding to samples of the comparison voltage; and a digital filter and decimator coupled to the clocked sampling latch and outputting serial data bits which form a digital representation corresponding to the output of the touch screen device. Additional circuits and systems are disclosed.

Abstract: A display panel includes multiple pixel elements for composing an image and a control circuit for accessing each pixel element. The control circuit includes a data line for conducting a luminance signal and a selection line for conducting a selection signal. Each pixel element includes a switch, a display cell, and a compensatory capacitor. The switch is connected to the data line and the selection line, such that the switch can selectively deliver the luminance signal to the display cell. The display cell is configured to adjust its light transmittance in response to the received luminance signal. Being connected to the switch and the display cell, the compensatory capacitor is configured to receive a compensation signal corresponding to a transition of the selection signal and for correcting a parasitic effect at the display cell.

Abstract: An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta analog to digital converter configured for direct connection to an analog output of a touch screen device, and further including an integrator circuit having an input coupled for receiving the analog output signal and outputting an integrated output voltage; a comparator coupled to the integrated output voltage and a first bias voltage and outputting a comparison voltage; a clocked sampling latch coupled to the comparison voltage and to a clock signal and outputting quantized data bits corresponding to samples of the comparison voltage; and a digital filter and decimator coupled to the clocked sampling latch and outputting serial data bits which form a digital representation corresponding to the output of the touch screen device. Additional circuits and systems are disclosed.

Abstract: A circuit and method for providing a current limiting feature in a low dropout (“LDO”) linear voltage regulator. A pass element generates an output voltage that is less than the input voltage. The pass element is normally enabled by an error amplifier that compares a feedback signal from the output of the pass element with a reference signal. However, the pass element may be enabled by a current limiting circuit that bypasses the error amplifier to limit the current generated at the output of the pass element.

Abstract: Circuitry (10-2) for limiting the maximum amount of current (IREF) flowing through a first electrode (DRAIN) of a first transistor (T1) includes an amplifier (14) having an output coupled by a conductor (19) to a control electrode of the first transistor and limiting circuitry (17) including reference current sensing circuitry (22,TSENSE) having a reference current source (IREF—SENSE). A reference current sensing transistor (TSENSE) has a control electrode coupled to the control electrode of the first transistor, a first electrode coupled to a terminal (20) of the reference current source, and a second electrode (SOURCE) coupled to a second electrode of the first transistor. A buffer (T2) has an input coupled to the terminal of the reference current source. The maximum amount is limited in accordance with the reference current source to prevent an increase in magnitude of voltage applied by the amplifier to the first transistor.

Abstract: Circuitry (10-2) for limiting the maximum amount of current (IREF) flowing through a first electrode (DRAIN) of a first transistor (T1) includes an amplifier (14) having an output coupled by a conductor (19) to a control electrode of the first transistor and limiting circuitry (17) including reference current sensing circuitry (22, TSENSE) having a reference current source (IREF—SENSE). A reference current sensing transistor (TSENSE) has a control electrode coupled to the control electrode of the first transistor, a first electrode coupled to a terminal (20) of the reference current source, and a second electrode (SOURCE) coupled to a second electrode of the first transistor. A buffer (T2) has an input coupled to the terminal of the reference current source. The maximum amount is limited in accordance with the reference current source to prevent an increase in magnitude of voltage applied by the amplifier to the first transistor.

Abstract: An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.

Abstract: An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.

Abstract: A voltage follower circuit including an input stage for generating a difference between the input signal and the output signal. An output circuit receiving the first signal and producing the output signal. A slew boost circuit includes a first transistor having a control electrode for receiving the input signal, a first electrode coupled to a first current source, and a second electrode coupled to a first supply voltage, a second transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to the first supply voltage, and a third transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to a second supply voltage.

Abstract: A voltage follower circuit including an input stage for generating a difference between the input signal and the output signal. An output circuit receiving the first signal and producing the output signal. A slew boost circuit includes a first transistor having a control electrode for receiving the input signal, a first electrode coupled to a first current source, and a second electrode coupled to a first supply voltage, a second transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to the first supply voltage, and a third transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to a second supply voltage.

Abstract: An elevator safety net system for preventing people, equipment, or debris from falling down commercial or residential elevator shafts during building construction, in each case avoiding injury. The net is a high-quality synthetic double-layer net with reinforced borders encased in fabric-sealed edges, and a plurality of steel grommets around the edges of the safety net. A plurality of safety nets may be suspended laterally up and down an elevator shaft before the elevator is installed, and this is done by screwing in eight eye bolts around the elevator shaft so that the safety net can be attached/suspended by snapping in closed steel hooks that connect the eye bolts to corresponding steel grommets of the net, thereby suspending the nets up and down the elevator shaft. The nets can be removed and reinstalled for future maintenance of the elevator shaft by snapping the hooks on and off the eye bolts screwed into the elevator shaft.

Abstract: A bus hold circuit that satisfies both the over-voltage tolerance and maximum leakage current ‘Ioff’ specification without incorporating a diode in pull-up path of a bus-hold circuit is disclosed herein. Specifically, the bus-hold circuit includes a first subcircuit portion operable to provide the bus-hold feature of the circuit connected to a second subcircuit portion. The second sub-circuit portion provides the over-voltage tolerance feature and minimizes the leakage current in the bus-hold circuit. The bus-hold circuit in accordance with the present invention is enhances the performance of the bus-hold current by eliminating the voltage drop across the diodes customarily included within known bus-hold circuit designs. Thereby, this implementation eliminates the negative diode effect on the minimum high sustaining bus-hold current (IBHH) at low supply voltages due to the voltage drop across the diode.

Abstract: A bus hold circuit that satisfies both the over-voltage tolerance and maximum leakage current ‘Ioff’ specification without incorporating a diode in pull-up path of a bus-hold circuit is disclosed herein. Specifically, the bus-hold circuit includes a first subcircuit portion operable to provide the bus-hold feature of the circuit connected to a second subcircuit portion. The second sub-circuit portion provides the over-voltage tolerance feature and minimizes the leakage current in the bus-hold circuit. The bus-hold circuit in accordance with the present invention is enhances the performance of the bus-hold current by eliminating the voltage drop across the diodes customarily included within known bus-hold circuit designs. Thereby, this implementation eliminates the negative diode effect on the minimum high sustaining bus-hold current (IBHH) at low supply voltages due to the voltage drop across the diode.

Abstract: The power supply selection control circuit includes: a first comparator; a second comparator; a first reference generator coupled to a first power supply node, and having a first reference output node coupled to a first input of the first comparator and to a first input of the second comparator; and a second reference generator coupled to a second power supply node, and having a second reference output node coupled to a second input of the first comparator and to a second input of the second comparator. The first comparator provides a logic low when the first power supply voltage is lower than the second power supply voltage. The second comparator provides a logic low when the second power supply voltage is lower than the first power supply voltage.

Abstract: An input circuit is provided which receives TTL voltage signals as input and transmits CMOS voltage signal levels. A separation transistor connected to a voltage divider network is included within the circuit to separate the two gates of a CMOS inverter from the TTL input such that one gate of the inverter is fully off when the other gate is on and fully on when the other gate is off. Thus internal ground voltage fluctuations during operation of the circuit are avoided.

Abstract: The disclosure relates to a circuit for compensation for ground glitches in an integrated circuit wherein there is provided a glitch fix circuit wherein a node is responsive to a negative shift in the level of ground relative to Vcc to turn on a transistor and drain current to ground from the input circuits to transistors in the circuit under control. A feedback circuit is provided which is out of phase with the circuit input of the circuit being controlled and which is one Von above ground. This feedback circuit inhibits the glitch fix circuit in the event that the increase in voltage difference between the input to the circuit being protected and ground is a result of a high input signal rather than noise which lowers the ground level.