Abstract: An efficient polling technique to attain improved system performance preserves the concept of polling, but instead of polling across system buses to the device, a poll is made within the processor's cache structure, which is typically internal to the processor complex or attached on a local isolated bus. The polling status location is mapped in the cachable address space of the processor. Hence, the polling occurs to a normal cachable location. When the device completes its task, it signals to the polling loop by invalidating the cache line corresponding to the poll location. The next time software tries to read the status value, the processor misses in its cache and automatically reloads the updated status value from the device. This causes the polling loop to exit and normal processing continues. The only bus traffic that results is that which is issued by the device to signal cache line invalidation and a subsequent processor initiated cache line reload.

Abstract: A method and system for rapid transfer of data between a system bus and an external device coupled together by a cable. A data processing system having at least one computer system, which includes an internal bus and an external device is provided wherein the internal bus is coupled to the external device via a cable. The external device includes an external processor capable of accessing data within the computer system. The data processing system also includes an interface module having a number of buffers for storing data, wherein the interface module is interposed along the cable between the computer and the external device. Control circuitry is included in the interface module for reading from and placing data into the buffers.