Abstract: A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.

Abstract: Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

Abstract: A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.

Abstract: Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

Abstract: Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

Abstract: An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent “pipes” from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the “fpr target”) are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand.

Abstract: A method for wrap detection in a microprocessor system, the system including a plurality of rename buffers. The method includes performing a two's complement subtraction of a completion pointer from a target pointer, wherein a carry out results from the subtraction. The method further includes comparing the carryout and a virtual bit associated with a location to produce a result. The result is compared to the most significant bit of the target pointer and if there is a match between the most significant bit of the second pointer and the result, an indication is made that the instruction may issue. A system for utilizing the above method of wrap detection includes a means for performing a two's complement subtraction of a completion pointer from a target pointer, wherein a carry out results from the two's complement subtraction.

Abstract: An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent “pipes” from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the “fpr target”) are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand.

Abstract: An FPSCR (Floating Point Status and Control Register) mechanism supports out-of-order floating point unit instruction execution. The FPSCR mechanism provides appropriate reporting of exceptions to a re-order buffer implemented within a data processing system to allow precise interrupts during out-of-order instruction execution. Additionally, the FPSCR mechanism allows for the retention of the appropriate status and control history information in an FPSCR rename buffer to allow the floating points status and control register to be maintained as though instructions were being executed in order. Additionally, the FPSCR mechanism generates the FPSCR's sticky exception status in concordance with reporting appropriate status to the previously mentioned re-order buffer and saving history into the FPSCR rename buffer.

Abstract: An FPSCR (Floating Point Status and Control Register) mechanism supports de-serialized floating point unit (FPU) instruction execution. The FPSCR mechanism provides for speculative execution of all FPU instructions. In particular, instructions that directly alter FPSCR data values may be executed speculatively. Instructions of this type which may be de-serialized include the move-from FPSCR instruction, the move-to-condition register from FPSCR instruction, the move-to FPSCR field immediate instruction, the move-to FPSCR field instruction, the move-to FPSCR bit 0 instruction, the move-to FPSCR bit 1 instruction, as well as FPU register-to-register instructions having a recording bit set. Speculative execution is implemented by providing an accurate working FPSCR at the time the speculatively executing instruction sources FPSCR data. Moreover, the FPSCR mechanism re-establishes the working FPSCR when exceptions occur, or speculative execution is cancelled.