Abstract: A method and system for providing a via structure for an integrated circuit is disclosed. The method and system includes providing a high conductivity metal that forms a metal structure consisting of the high conductivity metal. The method and system also includes a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole. The method and system also include providing a via plug material other than the high conductivity metal. The via plug material covers the high conductivity metal and substantially fills the via hole. The via plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is for gettering the high conductivity metal sputtered on the sidewalls of the via hole.

Abstract: A method and system for patterning a metal layer of a semiconductor device is disclosed. The method and system includes providing a material with an antireflective low dielectric constant hard mask layer (antireflective low k hard mask layer) on top of the metal layer, and providing a photoresist pattern on top of the anti-reflective low k hard mask layer. The method and system further includes etching of the anti-reflective low k hard mask layer and etching of the metal layer, wherein the photoresist is removed but the anti-reflective low k hard mask layer remains. In a preferred embodiment, the mask layer can also be applied at low temperatures (i.e., >300.degree.) to ensure that the physical properties of the integrated circuit are not affected. Finally, the low k material does not have to be removed after processing.

Abstract: A method and system for providing a via structure for a high conductivity metal of a integrated circuit is disclosed. In a first aspect the method and system comprises etching a photoresist material and a dielectric material down to the high conductivity metal to form a via hole. The via hole includes sputtered high conductivity metal on the sidewalls. The method and system further includes providing a via plug material within the via hole. The vial plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the dielectric material. In a second aspect, a via structure for an integrated circuit is disclosed in accordance with the present invention. The via structure includes a high conductivity metal and a dielectric material surrounding the high conductivity metal.

Abstract: In a final wafer sort (FWS) testing facility, the raw log-out data that is output by FWS test stations is augmented with additional differentiating data to thereby produce differentiable log-outs that can be sorted according to a variety of criteria including: product number or product family, time of test, specific wafer, specific production lot, intra-reticle site number, machine operator, and the specific swappable units of equipment that participated in the FWS testing. The differentiable log-outs are stored in a database and are periodically accessed by an automatic watchdog system that tests for exception conditions calling for immediate or long-term response. Corresponding alarm signals and trend reports are automatically generated and distributed to responsible personnel and/or reactive machine-systems as appropriate. The alarm distribution mechanism includes automatic paging of personnel by wireless beeper and/or e-mail.