Patents by Inventor Susan L. Gilfeather

Susan L. Gilfeather has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5522085
    Abstract: An arithmetic engine includes a first dual multiplier accumulator (MAC) for receiving input data and for producing first dual MAC output data. A second dual MAC is coupled in parallel to the first dual MAC. The second dual MAC receives the input data and produces second dual MAC output data. An adder array is coupled to both the first dual MAC and to the second dual MAC. The adder array receives the input data, the first dual MAC output data, and the second dual MAC output data and produces arithmetic engine output data. Each dual MAC comprises a multiplier cross point switch, multiplier registers, a register selector, and parallel multipliers. Each adder array comprises a cross point switch, adder registers, a register selector, adder, and condition code determiner.
    Type: Grant
    Filed: February 24, 1995
    Date of Patent: May 28, 1996
    Assignee: Motorola, Inc.
    Inventors: Calvin W. Harrison, Susan L. Gilfeather, John B. Gehman, Jr.
  • Patent number: 5473557
    Abstract: A complex arithmetic processor and method includes a host interface for distributing data, a left memory and a right memory each coupled to the host interface, and a Z memory coupled to the host interface. The left memory and the right memory store the data and the Z memory stores Z memory data. A right/left switch is coupled to the left memory and to the right memory and makes left memory a data source and a right memory a data destination in a first setting, and makes the right memory the data source and the left memory the data destination in a second setting. An arithmetic engine is coupled to the host interface, to the Z memory, and to the left and right memories. The arithmetic engine uses the data and the Z memory data to perform an operation on the data to produce a result.
    Type: Grant
    Filed: June 9, 1994
    Date of Patent: December 5, 1995
    Assignee: Motorola, Inc.
    Inventors: Calvin W. Harrison, Susan L. Gilfeather, John B. Gehman, Jr., James E. Greenwood, Jr., Bruce A. Fette
  • Patent number: 5459681
    Abstract: A special functions arithmetic logic unit (ALU) method and apparatus includes an ALU register, an ALU register value processor coupled to the ALU register for receiving and processing ALU register values to produce output data, and a normalizer. The normalizer receives and processes complex memory values to produce normalized output data independently of the output data from the ALU register value processor. The ALU register value processor includes a parser, combiner, polynomial divider, magnitude estimator, and a Hamming distance determiner. The normalizer includes an exponent determiner and first and second scalers for producing normalized X and Y data of the normalized output data.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: October 17, 1995
    Assignee: Motorola, Inc.
    Inventors: Calvin W. Harrison, Susan L. Gilfeather, John B. Gehman, Jr., Bruce A. Fette