Abstract: Disclosed are an automated data analysis system and method. They system provides a standardized data analysis request form that allows a user to select an experiment (e.g., a wafer-level based yield split lot (EWR) analysis, a lot-level based process change notification (PCN) analysis, and lot-level based tool/mask qualification analysis) and a data analysis for a specific process module of interest. For each specific data analysis request, the system identifies critical test parameters, which are grouped depending on in-line test levels and photolithography levels. The system links the analysis request to test data sources and automatically monitors the test data sources, searching for the critical test parameters. When the critical test parameters become available, the system automatically performs the requested analysis, generates a report of the analysis and publishes the report with optional drill downs to more detailed results.

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirection bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches.

Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches.

Abstract: Each section (e.g., 102) of the ring oscillator consists of three two-input NOR gates; one in the feedforward path (108), one in the feedback path (112), and one in the crossover path (110). The center frequency of the oscillator is controlled by enabling and disabling the appropriate gates, such that a single closed loop path is formed. The gates in the feedforward and crossover paths are directly enabled or disabled (to disable, either input is held high) from a control circuit (FIG. 2). The gates in the feedback path, however, are indirectly enabled and disabled. To enable a particular feedback path gate (e.g., 118), either the corresponding crossover gate (116) is disabled, or the corresponding feedforward gate is disabled (114) and the crossover gate (122) in the following section is enabled. The later causes the feedback gate (124) in the following section to be disabled, thereby removing the remaining sections (106) of the oscillator from the closed loop path.

Abstract: A voltage regulator for regulating the voltage at a first node, comprisinga first voltage supply;a first node;a first transistor with a control terminal connected to the first node;a circuit for varying the VBE voltage drop of the first transistor in accordance with whether the voltage level of the first voltage supply is above or below a threshold voltage and for continuously sinking current from the first transistor; anda circuit for varying the voltage level at the current-emitting terminal of the first transistor to counteract, in combination with the varying VBE voltage drop, the change in the voltage level of the first voltage supply.