Abstract: A digital system aligns a set of serial data receiver demultiplex circuits, thereby aligning the bits in the data words, while maintaining separate and optimally aligned data recovery clocks for each channel. The digital system generates a reference clock signal and one or more slave clock signals. Phase circuitry receives the slave clock signal and outputs a plurality of clock phase signals. A phase selection circuit receives the plurality of clock phase signals and selects an adjusted clock signal in response to a phase selection signal. A clock correlation circuit determines a phase difference between the reference clock signal and the adjusted clock signal and provides the phase selection signal to minimize the phase difference. The clock correlation circuit provides the phase selection signal from a counter.

Abstract: A digital system is provided with a means for achieving alignment between a set of serial data receiver demultiplex circuits, thereby achieving alignment of the bits in the data words, while maintaining the use of separate and therefore optimally aligned data recovery clocks for each channel signal. The digital system is provided with circuitry for generating a reference clock signal and clock circuitry for generating one or more slave clock signals. Phase circuitry is connected to receive the slave clock signal and has outputs for providing a plurality of clock phase signals. A phase selection circuit is connected to receive the plurality of clock phase signals. The phase selection circuit has an output for providing an adjusted clock signal selected from the plurality of clock phase signals in response to a phase selection signal.