Abstract: The present invention provides a method for use with program overlays, wherein code segments, along with data segments pertaining to the code segments, are transferred into a receiving memory segment. Program code is separated into common code and overlay code. The overlay code is then broken down into segments according to functionality, and the need to create segments that will fit into a receiving memory segment. An overlay control file is created for each segment, then a wrapper file. Linker command files are created for the common area and code area. The wrapper files and linker command files are used to create a common image file for the code/data. The common image is used to produce overlay sections, which are then concatenated together into one file. This one file is then loaded into memory for transfer of the overlays to a receiving memory area.

Abstract: The present invention provides an apparatus and method to reduce the memory footprint of a processor architecture by structuring processor code to be stored in an external device, and transferring into the processor certain code and associated data as it is needed. The processor code or algorithm is divided into a controlling piece and a working piece. The controlling piece can be located on a low-MIPS, high memory-footprint device, whereas the working piece can be located on a high-MIPS, low memory-footprint device. The working piece can also be broken down into phases or segments, which are put in a data store. The segments are then transferred, on an as-needed basis along with associated data, from the store into the constrained memory of the low memory-footprint device. Transfer is facilitated by a segment manager which can be processed from the low-MIPS device, or alternatively from the high-MIPS device.

Abstract: The present invention provides a method for use with program overlays, wherein code segments, along with data segments pertaining to the code segments, are transferred into a receiving memory segment. Program code is separated into common code and overlay code. The overlay code is then broken down into segments according to functionality, and the need to create segments that will fit into a receiving memory segment. An overlay control file is created for each segment, then a wrapper file. Linker command files are created for the common area and code area. The wrapper files and linker command files are used to create a common image file for the code/data. The common image is used to produce overlay sections, which are then concatenated together into one file. This one file is then loaded into memory for transfer of the overlays to a receiving memory area.

Abstract: The present invention provides an apparatus and method to reduce the memory footprint of a processor architecture by structuring processor code to be stored in an external device, and transferring into the processor certain code and associated data as it is needed. The processor code or algorithm is divided into a controlling piece and a working piece. The controlling piece can be located on a low-MIPS, high memory-footprint device, whereas the working piece can be located on a high-MIPS, low memory-footprint device. The working piece can also be broken down into phases or segments, which are put in a data store. The segments are then transferred, on an as-needed basis along with associated data, from the store into the constrained memory of the low memory-footprint device. Transfer is facilitated by a segment manager which can be processed from the low-MIPS device, or alternatively from the high-MIPS device.