Abstract: The present invention relates to a method, and a respective system, and computer program product for sending data packets along a predefined data path, wherein the receipt of a packet is acknowledged within a predefined time delay that was preset and tuned according to the duration of the send process via said data path. Packets that were sent along the data path are also entered into a pipeline. The pipeline is tuned to have a depth of a predetermined number of clock cycles that correlates to the predefined time delay for the receipt of an acknowledgement message. For a packet in the output registers of the pipeline it is checked if an acknowledge message for the packet was received. Otherwise the packet will be sent again. Especially, the pipeline can be used as a bus trace vehicle.

Abstract: The present invention relates to the processing of information in a computer with multiple stages wherein in each stage a particular, stage-specific work is done with or without stage-specific data. The present invention in particular adheres to the tracing of events which happen in each of these stages. In order to provide a method which generates trace information for work items which can be easier evaluated, it is proposed to perform the steps of: generating an entry in a trace pipeline for a work item; selecting a subset of trace information generated during the processing of said work item in a processing stage, adding said subset to said entry, and putting said entry to the next stage of said trace pipeline in every stage of said processing stages.

Abstract: The present invention relates to a method and system for transferring a stream of data from a first higher-speed subsystem of a computer to a plurality of lower speed subsystems, wherein the stream is structured in a sequence of blocks of different bit length, and a block is to be transferred to a specific one of said lower-speed subsystems. A corresponding method uses a queue for buffering the data, which includes control bits [c], [u], [k] to encode the further processing relevant for the association of the data block with a specific one of said lower-speed subsystems, when the queue entry is decoded at the output register of the queue.