Patents by Inventor Susan S. FAN
Susan S. FAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10615255Abstract: A method of fabricating a semiconductor structure includes forming a plurality of semiconductor fins disposed on a semiconductor substrate, wherein at least one of the fins is an unwanted fin including a semiconductor material; providing a conformal protective layer over the plurality of semiconductor fins; forming a mask having an opening over the unwanted fin; removing a portion of the unwanted fin to expose a fin spike; oxidizing the fin spike to form an oxidized semiconductor material; and removing the oxidized semiconductor material to expose a fin base.Type: GrantFiled: February 12, 2016Date of Patent: April 7, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., SAMSUNG ELECTRONICS CO., LTD.Inventors: Susan S. Fan, Dongseok Lee, David Moreau, Tenko Yamashita
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Patent number: 10586733Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: GrantFiled: January 2, 2019Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Publication number: 20190157140Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: ApplicationFiled: January 2, 2019Publication date: May 23, 2019Inventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Patent number: 10224239Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: GrantFiled: August 30, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Patent number: 10204827Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: GrantFiled: August 30, 2017Date of Patent: February 12, 2019Assignee: International Business Machines CorporationInventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Publication number: 20180019202Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: ApplicationFiled: August 30, 2017Publication date: January 18, 2018Inventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Publication number: 20180019203Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: ApplicationFiled: August 30, 2017Publication date: January 18, 2018Inventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Publication number: 20180019200Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: ApplicationFiled: July 12, 2016Publication date: January 18, 2018Inventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Patent number: 9859212Abstract: An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.Type: GrantFiled: July 12, 2016Date of Patent: January 2, 2018Assignee: International Business Machines CorporationInventors: Richard A. Conti, Jessica Dechene, Susan S. Fan, Son V. Nguyen, Jeffrey C. Shearer
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Publication number: 20170236722Abstract: A method of fabricating a semiconductor structure includes forming a plurality of semiconductor fins disposed on a semiconductor substrate, wherein at least one of the fins is an unwanted fin including a semiconductor material; providing a conformal protective layer over the plurality of semiconductor fins; forming a mask having an opening over the unwanted fin; removing a portion of the unwanted fin to expose a fin spike; oxidizing the fin spike to form an oxidized semiconductor material; and removing the oxidized semiconductor material to expose a fin base.Type: ApplicationFiled: February 12, 2016Publication date: August 17, 2017Inventors: Susan S. Fan, Dongseok Lee, David Moreau, Tenko Yamashita
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Patent number: 9368590Abstract: A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.Type: GrantFiled: November 6, 2013Date of Patent: June 14, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Susan S. Fan, Balasubramanian S. Haran, David V. Horak, Charles W. Koburger
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Publication number: 20140061799Abstract: A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.Type: ApplicationFiled: November 6, 2013Publication date: March 6, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Susan S. FAN, Balasubramanian S. HARAN, David V. HORAK, Charles W. KOBURGER
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Patent number: 8623730Abstract: A method is provided for fabricating a transistor. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.Type: GrantFiled: September 14, 2012Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Susan S. Fan, Balasubramanian S. Haran, David V. Horak, Charles W. Koburger, III
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Publication number: 20130178052Abstract: A method is provided for fabricating a transistor. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.Type: ApplicationFiled: September 14, 2012Publication date: July 11, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Susan S. FAN, Balasubramanian S. HARAN, David V. HORAK, Charles W. KOBURGER, II
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Publication number: 20130175619Abstract: A transistor includes a semiconductor layer, a gate spacer on the semiconductor layer, a gate dielectric comprising a first portion above the semiconductor layer and a second portion on sidewalls of the gate spacer, a work function metal layer comprising a first portion on the first portion of the gate dielectric and a second portion on sidewalls of the gate dielectric, a gate conductor on the first portion of the work function layer and abutting the second portion of the work function layer, a dielectric layer on the semiconductor layer and abutting the gate spacer, an oxide film above only one of the work function layer and the gate conductor, an oxide cap, source/drain regions, and a source/drain contact passing through the dielectric layer and contacting an upper surface of one of the source/drain regions. A portion of the source/drain contact is located directly on the oxide cap.Type: ApplicationFiled: January 6, 2012Publication date: July 11, 2013Applicant: International Business Machines CorporationInventors: Susan S. FAN, Balasubramanian S. HARAN, David V. HORAK, Charles W. KOBURGER, III