Patents by Inventor Susan S. Meredith

Susan S. Meredith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7194607
    Abstract: An adaptive arrangement including a command translation/ordering unit arranged to recognize and convert a first predetermined command unrecognizable/unsupported by an external recipient into a second predetermined command recognizable/supported by the external recipient. Such arrangement is further arranged to control a predetermined ordering of the converted second predetermined command with respect to other commands. The command translation/ordering unit may be arranged to control ordering such that all commands handled prior to the first predetermined command are completed prior to completion of the converted second predetermined command. Further, the command translation/ordering unit may be arranged to control ordering such that all commands handled after the first predetermined command are completed after completion of the converted second predetermined command.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: March 20, 2007
    Assignee: Intel Corporation
    Inventors: Eric J. Dahlen, Susan S. Meredith
  • Publication number: 20030189573
    Abstract: An adaptive arrangement including a command translation/ordering unit arranged to recognize and convert a first predetermined command unrecognizable/unsupported by an external recipient into a second predetermined command recognizable/supported by the external recipient. Such arrangement is further arranged to control a predetermined ordering of the converted second predetermined command with respect to other commands. The command translation/ordering unit may be arranged to control ordering such that all commands handled prior to the first predetermined command are completed prior to completion of the converted second predetermined command. Further, the command translation/ordering unit may be arranged to control ordering such that all commands handled after the first predetermined command are completed after completion of the converted second predetermined command.
    Type: Application
    Filed: March 31, 2003
    Publication date: October 9, 2003
    Inventors: Eric J. Dahlen, Susan S. Meredith
  • Patent number: 6567883
    Abstract: An adaptive arrangement including a command translation/ordering unit arranged to recognize and convert a first predetermined command unrecognizable/unsupported by an external recipient into a second predetermined command recognizable/supported by the external recipient. Such arrangement is further arranged to control a predetermined ordering of the converted second predetermined command with respect to other commands. The command translation/ordering unit may be arranged to control ordering such that all commands handled prior to the first predetermined command are completed prior to completion of the converted second predetermined command. Further, the command translation/ordering unit may be arranged to control ordering such that all commands handled after the first predetermined command are completed after completion of the converted second predetermined command.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: May 20, 2003
    Assignee: Intel Corporation
    Inventors: Eric J. Dahlen, Susan S. Meredith
  • Patent number: 6502154
    Abstract: A bus bridging method, a bus bridge and a bus agent are described. In a bus agent provides to a bus bridge a read data request targeting a data source bridged by the bus bridge. The read data request includes a read address indicating a starting storage location of the requested data, and a read size indicator indicating the size of the requested data. The bus bridge, in response, facilitates provision of the requested data to the bus agent. The facilitation includes streaming buffered ones of the requested data to the bus agent through one or more successive streaming connections to the bus bridge by the bus agent.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: December 31, 2002
    Assignee: Intel Corporation
    Inventors: Susan S. Meredith, Warren R. Morrow, Wendell S. Wenjen, John Baudrexl, David L. Chalupsky, Dave B. Minturn
  • Patent number: 6078980
    Abstract: A computer system includes a bus, a first bus device, a core circuit and a second circuit. The first bus device is coupled to the bus and adapted to finish a first indication of data to a portion of a bus beginning at a first clock cycle. The bus is capable of skewing the first indication to produce a second indication of the data at another portion of the bus beginning at another clock cycle. The second circuit is coupled to the bus and is adapted to receive an indication of a selected latency time. The second circuit is also adapted to transfer the data to the core circuit in response to the second indication and regulate the transfer so that the circuit receives the data beginning at the selected latency time after the first clock cycle.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: June 20, 2000
    Assignee: Intel Corporation
    Inventors: Kenneth C. Holland, David M. Lee, Susan S. Meredith
  • Patent number: 6021451
    Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: February 1, 2000
    Assignee: Intel Corporation
    Inventors: D. Michael Bell, Mark A. Gonzales, Susan S. Meredith
  • Patent number: 5835739
    Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: November 10, 1998
    Assignee: Intel Corporation
    Inventors: D. Michael Bell, Mark A. Gonzales, Susan S. Meredith
  • Patent number: 5675794
    Abstract: An apparatus for configuring multiple agents in a computer system includes a first storage device for storing a set of configuration values and a second storage device for capturing the set of configuration values from the bus. These configuration values are driven onto the bus and retrieved from the bus by interface logic within the apparatus. The interface logic drives the configuration values onto the bus when a register within the apparatus is activated. At system power-on, the first storage device defaults to a first set of values. These values are then driven onto the bus and retrieved by each agent on the bus, including the apparatus of the present invention. This first set of values provides the system with the necessary parameters to access and execute certain initialization program(s). These initialization programs can modify the configuration values stored in the first storage device.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: October 7, 1997
    Assignee: Intel Corporation
    Inventor: Susan S. Meredith
  • Patent number: 5546546
    Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.
    Type: Grant
    Filed: May 20, 1994
    Date of Patent: August 13, 1996
    Assignee: Intel Corporation
    Inventors: D. Michael Bell, Mark A. Gonzales, Susan S. Meredith
  • Patent number: 5535340
    Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Decoding circuitry within the bridge issues a deferred response if the request can be deferred. This deferred response is returned to the originating agent on the first bus, thereby informing the originating agent that the request will be serviced at a later time. Bus control circuitry coupled to the outbound request queue removes requests from the outbound request queue and executes them on the second bus. The bus control circuitry receives a response from the destination agent on the second bus in response to the execution of the outbound request. This response is returned to the originating agent either immediately or after passing through an inbound request queue.
    Type: Grant
    Filed: May 20, 1994
    Date of Patent: July 9, 1996
    Assignee: Intel Corporation
    Inventors: D. Michael Bell, Mark A. Gonzales, Susan S. Meredith