Patents by Inventor Susan Tovar

Susan Tovar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Insulating and capping structure with preservation of the low dielectric constant of the insulating layer
    Patent number: 6383950
    Abstract: An insulating and capping structure of an integrated circuit is formed on a semiconductor wafer. An insulating layer is formed on the semiconductor wafer, and the insulating layer is comprised of a dielectric material having a low dielectric constant that is less than about 4.0 and having chemical bonds that are chemically reactive with a predetermined reactant. A reaction barrier layer is formed on the insulating layer, and the reaction barrier layer is comprised of a material that is not chemically reactive with the predetermined reactant. A capping layer is formed on the reaction barrier layer, and the capping layer is formed using the predetermined reactant.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: May 7, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Suzette K. Pangrle, Minh Van Ngo, Susan Tovar
  • Insulating and capping structure with preservation of the low dielectric constant of the insulating layer
    Patent number: 6326692
    Abstract: An insulating and capping structure of an integrated circuit is formed on a semiconductor wafer. An insulating layer is formed on the semiconductor wafer, and the insulating layer is comprised of a dielectric material having a low dielectric constant that is less than about 4.0 and having chemical bonds that are chemically reactive with a predetermined reactant. A reaction barrier layer is formed on the insulating layer, and the reaction barrier layer is comprised of a material that is not chemically reactive with the predetermined reactant. A capping layer is formed on the reaction barrier layer, and the capping layer is formed using the predetermined reactant.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: December 4, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Suzette K. Pangrle, Minh Van Ngo, Susan Tovar
  • Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines
    Patent number: 6171947
    Abstract: In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, the substrate and interconnect lines are annealed prior to deposition of an ILD. A post annealing SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. Additionally, during deposition, minor adjustments are made to deposition temperature and process pressure to control the optical characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: January 9, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Suzette K. Pangrle, Paul R. Besser, Minh Van Ngo, Stephan Keetai Park, Susan Tovar