Abstract: According to one exemplary embodiment, a method for isolating a failure site in a leaky wordline in a memory array includes dividing said leaky wordline into an initial leaky wordline portion and an initial non-leaky wordline portion, where the initial leaky wordline portion has wordline-to-substrate leakage. The initial leaky wordline portion can be determined by using a passive voltage contrast procedure to illuminate the initial leaky wordline portion. The method further includes performing a number of division and identification cycles on the initial leaky wordline portion to determine a final leaky wordline portion. According to this exemplary embodiment, the final leaky wordline portion comprises a predetermined number of memory cells. The method further includes performing a cutting and imaging procedure on the final leaky wordline portion to isolate the failure site.

Abstract: Gas-assisted etching (GAE) for integrated circuit dies is enhanced via a method and system that enable halide-assisted etching of dies having copper material. According to an example embodiment of the present invention, an integrated circuit die having copper is etched using a focused ion beam (FIB) and a halide etch gas, such as chlorine. A selected amount of oxygen-containing gas is supplied to the die to react with the halide and prevent the corrosion of exposed copper material in the die. In this manner, the benefits of halide-assisted etching are realized while inhibiting the corrosion of copper that typically occurs with integrated circuit dies having copper material.

Abstract: An apparatus for x-raying a semiconductor device which includes semiconductor material and conductive material, the apparatus including a source of x-rays, a filter for receiving x-rays from the source of x-rays and allowing transmission of x-rays to the device, the filter having an atomic number greater than the atomic number of the conductive material of the device, and an x-ray imager for receiving x-rays from the device.

Abstract: The present invention provides a method for modifying a C4 device, the device including a circuit, a polyimide layer, and a plurality of solder bumps in the active region of the C4 device. The method includes removing the polyimide layer using a plasma etch, the plasma etch comprising a mixture of oxygen and an inert gas; modifying the circuit; and cleaning the modified C4 device with a reactive flux. By mixing the oxygen with an inert gas, the oxidation of the solder bumps due to the plasma etch are reduced. Because the top layer features are now readily visible, circuit structures are more easily located, and modification can be more easily performed and with more accuracy. In the preferred embodiment, the device is then cleaned with a reactive flux, which removes any oxidation layer which has formed on the solder bumps. In this manner, circuit modification may be performed more quickly while also minimizing the oxidation of the solder bumps.

Abstract: Aspects for performing decapsulation of multi-chip devices are presented. One aspect includes removing a top die of the multi-chip device without employing a wet chemical etch and removing residual attach and package materials to expose a bottom die of the multi-chip device. An alternate aspect includes utilizing mechanical polishing and wet chemical etching to remove a top die of the multi-chip device, and exposing a bottom die through chemical decapsulation to allow failure analysis of the bottom die. A Flash memory die as a top die and a static random access memory (SRAM) die as a bottom die are included as a multi-chip device capable of decapsulation through these aspects.