Abstract: Disclosed are three-dimensional (3D) semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the substrate, and vertical channel structures that fill vertical channel holes that penetrate the stack structure. Each of the vertical channel structures includes a vertical semiconductor pattern and a data storage pattern that surrounds the vertical semiconductor pattern. The data storage pattern includes a first gate dielectric layer, a ferroelectric pattern, a first channel dielectric layer, and a second channel dielectric layer that are sequentially provided on an inner sidewall of each of the vertical channel holes.

Abstract: A semiconductor device including a peripheral circuit structure, a cell structure including gate electrodes and stacked on the peripheral circuit structure, the cell structure including a cell region, a connection region, and a peripheral circuit connection region, the cell structure, a plurality of channel structures extending in a vertical direction through the gate electrodes in the cell region, each of the plurality of channel structures including a first end portion close to the peripheral circuit structure and a second end portion opposite to the first end portion, and a common source layer connected to the second end portion of each of the channel structures in the cell region may be provided.

Abstract: A semiconductor device includes: a substrate; a gate stacking structure that includes interlayer insulating layers and gate electrodes that are alternately stacked on the substrate; a channel structure that penetrates the gate stacking structure and extends in a first direction, and includes a channel layer connected to the substrate and a ferroelectric layer that surrounds the channel layer; a charge inflow pattern disposed on a lateral side of the ferroelectric layer and spaced apart in the first direction; and an insulation pattern disposed between the charge inflow pattern and the gate electrodes and that surrounds an exterior side, a lower side, and an upper side of the charge inflow pattern.

Abstract: A semiconductor device includes: a substrate, a gate stacking structure that includes a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on the substrate, a channel layer that extends in a first direction and into the gate stacking structure, where the channel layer is electrically connected to the substrate, a channel insulating layer that at least partially surrounds the channel layer, and a plurality of dielectric layers that are between the channel insulating layer and the plurality of gate electrodes, extend along a circumference of the channel layer, and are spaced apart from each other in the first direction, where each of the plurality of dielectric layers includes: a ferroelectric pattern that at least partially surrounds the channel insulating layer, and an anti-ferroelectric pattern that at least partially surrounds the ferroelectric pattern.

Abstract: A method of operating a memory device, the method including: applying a program inhibition voltage to an unselected bit line in a first program loop of a plurality of program loops; applying a program permission voltage to a selected bit line in the first program loop; applying a pass voltage to an unselected word line in the first program loop; applying a program voltage to a selected word line in the first program loop; applying a pulse voltage having a polarity opposite to a polarity of the program voltage to the selected word line after applying the program voltage to the selected word line, in the first program loop; and applying a verification voltage to the selected word line after applying the pulse voltage to the selected word line, in the first program loop.

Abstract: A three-dimensional semiconductor memory device may include a stack including gate electrodes and insulating layers, which are alternatingly stacked on a substrate, vertical channel structures penetrating the stack, and data storage patterns between the stack and the vertical channel structures. The data storage patterns may be spaced apart from each other in a direction perpendicular to a top surface of the substrate, and each of the data storage patterns may include a ferroelectric pattern, an anti-ferroelectric pattern, and a first insulating pattern.

Abstract: The present disclosure relates to a semiconductor device and a data storage system including the device. The semiconductor device has a substrate including a cell array region and a contact region. In the cell array region the semiconductor device has a first horizontal conductive layer, a gate stacking structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate. A channel structure extends in a direction crossing into the substrate by penetrating the gate stacking structure in the cell array region, and includes a channel layer connected to the substrate. Surrounding the channel layer is a ferroelectric layer. The first horizontal conductive layer is not in direct contact with the channel layer due to a dummy pattern positioned on the first horizontal conductive layer and disposed between the substrate and the ferroelectric layer.

Abstract: A semiconductor device includes a stacked structure including a plurality of gate lines and a plurality of insulation patterns that are alternately stacked in a vertical direction, where the stacked structure defines a vertical hole that extends into the stacked structure and in the vertical direction, a channel film that extends into a vertical hole, and a multiple dielectric layer structure between the channel film and the stacked structure, where the multiple dielectric layer structure includes a plurality of interlayer dielectric layers and a plurality of ferroelectric layers that are alternately stacked and extend from the channel film toward the stacked structure, and where an inner ferroelectric layer of the plurality of ferroelectric layers is thicker than an outer ferroelectric layer of the plurality of ferroelectric layers.

Abstract: A semiconductor device may include first conductive lines on a substrate and spaced apart from each other in a first direction, second conductive lines spaced apart from the first conductive lines in a second direction, third conductive lines spaced apart from the second conductive lines in the second direction, gate electrodes between the first, second and third conductive lines and extending in the first direction, ferroelectric patterns on respective side surfaces of the gate electrodes, gate insulating patterns on the respective side surfaces of the gate electrodes and spaced apart from the respective side surfaces of the gate electrodes with the ferroelectric patterns respectively therebetween, and channel patterns extending along respective side surfaces of the gate insulating patterns. Each of the channel patterns may be electrically connected to the second conductive lines, respectively, and may be electrically connected to the first conductive lines or the third conductive lines, respectively.

Abstract: A semiconductor device includes a gate stack structure including alternately stacked insulating patterns and conductive patterns; a memory channel structure extending through the gate stack structure; and a bit line pad on the memory channel structure, wherein the memory channel structure includes a variable resistance layer, a channel layer surrounding the variable resistance layer, and a channel insulating layer surrounding the channel layer, and a bottom surface of the bit line pad contacts a top surface of the variable resistance layer, a top surface of the channel layer, and a top surface of the channel insulating layer.