Abstract: A semiconductor device may include first conductive lines on a substrate and spaced apart from each other in a first direction, second conductive lines spaced apart from the first conductive lines in a second direction, third conductive lines spaced apart from the second conductive lines in the second direction, gate electrodes between the first, second and third conductive lines and extending in the first direction, ferroelectric patterns on respective side surfaces of the gate electrodes, gate insulating patterns on the respective side surfaces of the gate electrodes and spaced apart from the respective side surfaces of the gate electrodes with the ferroelectric patterns respectively therebetween, and channel patterns extending along respective side surfaces of the gate insulating patterns. Each of the channel patterns may be electrically connected to the second conductive lines, respectively, and may be electrically connected to the first conductive lines or the third conductive lines, respectively.

Abstract: A semiconductor device includes a gate stack structure including alternately stacked insulating patterns and conductive patterns; a memory channel structure extending through the gate stack structure; and a bit line pad on the memory channel structure, wherein the memory channel structure includes a variable resistance layer, a channel layer surrounding the variable resistance layer, and a channel insulating layer surrounding the channel layer, and a bottom surface of the bit line pad contacts a top surface of the variable resistance layer, a top surface of the channel layer, and a top surface of the channel insulating layer.