Abstract: A disclosed pre-driver circuit includes multiple signal generation stages configured to receive different bias voltages from local switching bias circuit(s). In some embodiment, pre-driver circuit has multiple switching bias circuits, each with a bias voltage node connected to a corresponding stage. In other embodiments, the pre-driver circuit has a single switching bias circuit with multiple bias voltage nodes and a multi-input/multi-output multiplexor with inputs connected to the bias voltage nodes and outputs connected to the stages. The switching bias circuit(s) and a primary inverter in each stage all receive the same input signal. When this input signal transitions, the switching bias circuit(s) supply bias voltages to the stages and the primary inverters turn on in sequence and slowly, thereby ensuring that pre-driver signals generated by the different stages transition in sequence and at a relatively slow rate. Once the last pre-driver signal transitions, the switching bias circuit(s) turn off.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.

Abstract: A disclosed pre-driver includes multiple signal generation stages and a switching bias circuit with a first switch and a second switch. The first switch and primary inverters in each of the stages all receive the same input signal. When the input signal transitions, the first switch turns on the bias circuit to supply a bias voltage to each of the stages. However, the primary inverters do not concurrently turn on. Instead, due to the bias voltage and some additional circuitry within each stage, the primary inverters turn on in sequence and slowly, thereby ensuring that pre-driver signals generated and output by the different stages, respectively, transition in sequence and at a relatively slow rate. Once the last pre-driver signal transitions, the second switch turns off the switching bias circuit. Optionally, a selected one of multiple bias voltages could be used in order to tune delay and transition times.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.

Abstract: A calibration circuit is connected to an input/output driver, a voltage bias generator is connected to the calibration circuit and the input/output driver, and a temperature sensor is connected to the voltage bias generator. The calibration circuit and input/output driver each include a bank of resistors and corresponding switches. Bodies of the switches are connected to the voltage bias generator, and the switches are biased by a bias signal output from the voltage bias generator. The calibration circuit includes a comparator device connected to the switches and to a reference resistor. Activation and deactivation of selected ones of the switches is made to match the reference resistor. Also, the voltage bias generator adjusts the bias signal when a temperature change is sensed by the temperature sensor. Thus, the switches change current flow as the bias signal changes, without changing which of the switches are activated or deactivated.

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.

Abstract: At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.

Abstract: At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.

Abstract: A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.

Abstract: A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.

Abstract: A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.

Abstract: A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values.

Abstract: A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values.

Abstract: A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.