Abstract: A maximum likelihood detector and a method for maximum likelihood detection of digital samples of channel output of data recorded as analog signals representing a finite number of states. The method comprises, first, programming at least two numerical metric coefficients. The coefficients are respectively applied to each sequential digital sample to generate alternative metrics, and each respective alternative metric is compared to a previous metric based on a previous digital sample. Based on the comparison, one of a plurality of provided metrics is selected which minimizes the mean squared error with respect to the previous metric. Then, the one of the finite number of states represented by the selected metric is identified, and a maximum likelihood path memory is set to a maximum likelihood state dictated by the identified one of the finite states, thereby detecting the recorded analog signals.

Abstract: A maximum likelihood detector and a method for maximum likelihood detection of digital samples of channel output of data recorded as analog signals representing a finite number of states. The method comprises, first, providing at least two numerical metric coefficients. The coefficients are derived from the difference between metrics directly associating “0” and “1” states of the recorded signal. The coefficients are respectively applied to each sequential digital sample to generate alternative metrics, and each respective alternative metric is compared to a previous difference metric based on a previous digital sample. Based on the comparison, one of a plurality of provided metrics is selected which minimizes the mean squared error with respect to the previous metric.

Abstract: An improved multi-bit error correction system. The inventive error correcting system performs a fast error correction operation on individual bits within multi-bit modules. In a specific implementation, the invention uses Hamming codes and divides an n times m bit data word into m modules, with each module having n bits. Next, the ith bits of each module are combined to form a set of parity bits. Syndrome bits are generated from the parity bits and used to locate errors in the bits and provide an indication of same. Finally, errors in the bits are corrected in a conventional manner to provide corrected data bits.

Abstract: A soft error correction technique and system for an odd weight row error correction code comprising a memory for storing a data word and its associated check bits and a control circuit for reading and inverting the data word and the check bit stored in memory. The system also comprises an inversion circuit for selectively reinverting the check bits. In a specific implementation, the check bit inversion circuit includes a plurality of Exclusive Or gates. A first input of each Exclusive Or gate is connected to receive the check bit from memory and a second input is connected to receive a control bit from a central processing unit via a software accessible control register. The inverted data word and the selectively reinverted check bit are input to an odd weight row error correcting circuit to correct a detected bit error. A method for correcting data errors for an odd weight row error correction system is also provided.