Patents by Inventor Susheel G. Jadhav

Susheel G. Jadhav has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11715928
    Abstract: An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 1, 2023
    Assignee: Intel Corporation
    Inventors: Priyanka Dobriyal, Susheel G. Jadhav, Ankur Agrawal, Quan A. Tran, Raiyomand F. Aspandiar, Kenneth M. Brown
  • Publication number: 20210066882
    Abstract: An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Applicant: INTEL CORPORATION
    Inventors: Priyanka Dobriyal, Susheel G. Jadhav, Ankur Agrawal, Quan A. Tran, Raiyomand F. Aspandiar, Kenneth M. Brown
  • Publication number: 20160260679
    Abstract: Apparatuses, processes, and systems related to an interconnect with an increased z-height and decreased reflow temperature are described herein. In embodiments, an interconnect may include a solder ball and a solder paste to couple the solder ball to a substrate. The solder ball and/or solder paste may be comprised of an alloy with a relatively low melting point and an alloy with a relatively high melting point.
    Type: Application
    Filed: March 27, 2014
    Publication date: September 8, 2016
    Applicant: Intel Corporation
    Inventors: Kabirkumar J. Mirpuri, Hongjin Jiang, Tyler N. Osborn, Rajen S. Sidhu, Ibrahim Bekar, Susheel G. Jadhav
  • Patent number: 8733620
    Abstract: A solder is deposited on a heat sink. The solder is first reflowed at a first temperature that is below about 120° C. The solder is second heat aged at a temperature that causes the first reflowed solder to have an increased second reflow temperature. The heat aging process results in less compressive stress in a die that uses the solder as a thermal interface material. The solder can have a composition that reflows and adheres to the die and the heat sink without the use of organic fluxes.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Mukul Renavikar, Susheel G. Jadhav
  • Patent number: 7955900
    Abstract: Some embodiments of the invention include a coated thermal interface to bond a die with a heat spreader. The coated thermal interface may be used to bond the die with the heat spreader without flux. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: June 7, 2011
    Assignee: Intel Corporation
    Inventors: Susheel G. Jadhav, Carl Deppisch
  • Patent number: 7553702
    Abstract: An integrated heat spreader and die coupled with solder are disclosed herein. The heat spreader may have solder reservoirs. Additionally, the heat spreader and die may be coupled during a reflow process where the gaseous pressure surrounding the integrated heat spreader and the die is varied.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: June 30, 2009
    Assignee: Intel Corporation
    Inventors: Thomas J Fitzgerald, Mukul P Renavikar, Susheel G Jadhav
  • Patent number: 7485495
    Abstract: Integrated heat spreader and die coupled with solder in a manner forming an intermetallic compound having a higher liquidus temperature than the liquidus temperature of the solder used to create the intermetallic compound are described herein.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: February 3, 2009
    Assignee: Intel Corporation
    Inventors: Mukul P. Renavikar, Susheel G. Jadhav
  • Patent number: 7239517
    Abstract: Integrated heat spreader and die coupled with solder. The heat spreader may have solder reservoirs. Additionally, the heat spreader and die may be coupled during a reflow process where the gaseous pressure surrounding the integrated heat spreader and the die is varied.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: July 3, 2007
    Assignee: Intel Corporation
    Inventors: Thomas J. Fitzgerald, Mukul P. Renavikar, Susheel G. Jadhav
  • Patent number: 7220622
    Abstract: Disclosed are embodiments of a method of attaching a die to a substrate and a heat spreader to the die in a single heating operation. A number of conductive bumps extending from the die may also be reflowed during this heating operation. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Susheel G. Jadhav, Daoqiang Lu
  • Patent number: 7183641
    Abstract: Integrated heat spreader and die coupled with solder in a manner forming an intermetallic compound having a higher liquidus temperature than the liquidus temperature of the solder used to create the intermetallic compound are described herein.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Mukul P. Renavikar, Susheel G. Jadhav
  • Patent number: 7164585
    Abstract: An apparatus and system, as well as fabrication methods therefor, may include a die having a surface and a primary material comprising tin, pure tin, or substantially pure tin coupled to the surface. A heat dissipating element may be coupled to the primary material.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: January 16, 2007
    Assignee: Intel Corporation
    Inventors: Susheel G. Jadhav, Carl Deppisch, Fay Hua
  • Publication number: 20040190263
    Abstract: An apparatus and system, as well as fabrication methods therefor, may include a die having a surface and a primary material comprising tin, pure tin, or substantially pure tin coupled to the surface. A heat dissipating element may be coupled to the primary material.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Applicant: Intel Corporation
    Inventors: Susheel G. Jadhav, Carl Deppisch, Fay Hua