Abstract: A time-interleaved analog to digital converter (ADC) circuit includes an input signal amplitude detector configured to determine an input signal amplitude of an analog input signal, a multi-tone signal generator configured to generate a plurality of analog and digital sinusoidal signals having an amplitude dependent on the determined input signal amplitude, and an analog input summing module configured to provide a summed output analog signal from the analog input signal and the analog sinusoidal signals. A time-interleaved ADC has an input coupled to receive the summed output analog signal from the analog input summing module and configured to provide a timing skew-calibrated digital output signal from the summed output analog signal. A digital output subtractor module is configured to provide a digital output signal at an output of the circuit from the digital output signal from the time-interleaved ADC and the digital sinusoidal signals from the multi-tone signal generator.

Abstract: A low dropout regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplification circuit, and an output circuit. The PTAT circuit outputs one current, and the amplification circuit outputs one or more currents. The one or more currents are outputted by the amplification circuit based on collector-emitter voltages associated with transistors of the PTAT circuit. Alternatively, the one or more currents are outputted by the amplification circuit based on the current outputted by the PTAT circuit and the collector-emitter voltages associated with the transistors of the PTAT circuit. The output circuit generates one or more output voltages based on at least one of a base-emitter voltage associated with a transistor of the PTAT circuit and a current of the one or more currents outputted by the amplification circuit.

Abstract: A low dropout regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplification circuit, and an output circuit. The PTAT circuit outputs one current, and the amplification circuit outputs one or more currents. The one or more currents are outputted by the amplification circuit based on collector-emitter voltages associated with transistors of the PTAT circuit. Alternatively, the one or more currents are outputted by the amplification circuit based on the current outputted by the PTAT circuit and the collector-emitter voltages associated with the transistors of the PTAT circuit. The output circuit generates one or more output voltages based on at least one of a base-emitter voltage associated with a transistor of the PTAT circuit and a current of the one or more currents outputted by the amplification circuit.

Abstract: An electronic system comprising a voltage-to-current converter and a proportional-to-absolute-temperature (PTAT) circuit is disclosed. The voltage-to-current converter is configured to receive one of a control voltage, a supply voltage, a scaled-down version of the control voltage, and a scaled-down version of the supply voltage, and generate a set of currents. The PTAT circuit is coupled with the voltage-to-current converter such that each current of the set of currents is one of sourced to the PTAT circuit and sank from the PTAT circuit. Further, the PTAT circuit is configured to receive at least one of the supply voltage and the control voltage, and generate a set of reference voltages. The control voltage is generated based on the set of reference voltages and the supply voltage.

Abstract: A bandgap reference voltage generator can include a bandgap core circuit configured to output at least one control voltage. The bandgap reference voltage generator can further include feedback circuitry that can be configured to receive a control voltage outputted by the bandgap core circuit or another control voltage generated based on the control voltage, and output a current. The current can be outputted such that the current is sourced to or sank from the bandgap core circuit. The feedback circuitry can be further configured to generate a bandgap reference voltage. When the current is sourced to the bandgap core circuit, the bandgap reference voltage can be greater than a threshold value. Similarly, when the current is sank from the bandgap core circuit, the bandgap reference voltage can be less than the threshold value.

Abstract: An integrated circuit (IC) includes a self-biased circuit and a start-up circuit for the self-biased circuit. The self-biased circuit generates a start-up indicator signal and an output signal. The start-up indicator signal indicates whether the self-biased circuit has started up. The start-up circuit includes a comparator, a start-up controller, and a peak controller. The comparator compares the start-up indicator signal with a reference signal generated based on supply voltages, and generates a comparison signal. The start-up controller controls a start-up of the self-biased circuit when the comparison signal is at a first logic state. Further, when the comparison signal transitions from the first logic state to a second logic state, the peak controller controls the output signal to maintain one of a voltage level and a current level of the output signal below a peak limit.

Abstract: A bandgap reference voltage generator can include a bandgap core circuit configured to output at least one control voltage. The bandgap reference voltage generator can further include feedback circuitry that can be configured to receive a control voltage outputted by the bandgap core circuit or another control voltage generated based on the control voltage, and output a current. The current can be outputted such that the current is sourced to or sank from the bandgap core circuit. The feedback circuitry can be further configured to generate a bandgap reference voltage. When the current is sourced to the bandgap core circuit, the bandgap reference voltage can be greater than a threshold value. Similarly, when the current is sank from the bandgap core circuit, the bandgap reference voltage can be less than the threshold value.

Abstract: An electronic system comprising a voltage-to-current converter and a proportional-to-absolute-temperature (PTAT) circuit is disclosed. The voltage-to-current converter is configured to receive one of a control voltage, a supply voltage, a scaled-down version of the control voltage, and a scaled-down version of the supply voltage, and generate a set of currents. The PTAT circuit is coupled with the voltage-to-current converter such that each current of the set of currents is one of sourced to the PTAT circuit and sank from the PTAT circuit. Further, the PTAT circuit is configured to receive at least one of the supply voltage and the control voltage, and generate a set of reference voltages. The control voltage is generated based on the set of reference voltages and the supply voltage.

Abstract: A technique is directed for managing entitlements within a real-time telemetry system. In an embodiment, access to entitlements is organized between an entitlement management service and an entitlement retrieval service. The entitlement management service may permit users to manage users and roles. The entitlement retrieval service may retrieve logged-in user's entitlements on a restricted basis using the information in an authorization token. The system may maintain separation between the entitlement management application programming interface (API) and entitlement retrieval API within the entitlement service, such that separation between entitlement management APIs, entitlement retrieval APIs, and entitlement enforcements may be enforced.

Abstract: A switched-capacitor amplifier circuit includes multiple switched-capacitor networks, an amplifier, and multiple reset circuits. The switched-capacitor networks are configured to receive respective input voltages during a sampling phase, and generate sampled voltages. During an amplification phase, the amplifier is coupled with the switched-capacitor networks, and is configured to receive the sampled voltages. The amplifier is further configured to generate output voltages. During the sampling phase, the amplifier is coupled with the reset circuits, and is further configured to receive divided voltages such that the amplifier is reset. The reset circuits are configured to receive and provide a common-mode voltage and the output voltages to the amplifier. The divided voltages are generated based on the common-mode voltage and the output voltages. Each reset circuit includes at least one of a resistor and a capacitor.

Abstract: A switched-capacitor amplifier circuit includes multiple switched-capacitor networks, an amplifier, and multiple reset circuits. The switched-capacitor networks are configured to receive respective input voltages during a sampling phase, and generate sampled voltages. During an amplification phase, the amplifier is coupled with the switched-capacitor networks, and is configured to receive the sampled voltages. The amplifier is further configured to generate output voltages. During the sampling phase, the amplifier is coupled with the reset circuits, and is further configured to receive divided voltages such that the amplifier is reset. The reset circuits are configured to receive and provide a common-mode voltage and the output voltages to the amplifier. The divided voltages are generated based on the common-mode voltage and the output voltages. Each reset circuit includes at least one of a resistor and a capacitor.

Abstract: A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), at least one conversion circuit, and at least one amplifier such that a number of conversion circuits and a number of amplifiers is less than a number of DACs. Each DAC is configured to receive an analog input signal in non-overlapping durations of a clock signal and generate a corresponding analog output signal. At least one of the conversion circuits is coupled with at least two DACs, and each conversion circuit is configured to perform conversion operation on a corresponding analog output signal to generate digital signals. At least one of the amplifiers is coupled with at least two DACs, and each amplifier is configured to perform amplification operation on a corresponding analog output signal.

Abstract: A sub-ranging analog-to-digital converter (ADC) includes a coarse ADC and a fine ADC that receives a set of coarse signals from the coarse ADC. The fine ADC includes multiple digital-to-analog converters (DACs) and multiple converters such that a number of converters is less than a number of DACs. The DACs and the converters function in a partial time-interleaved manner where each DAC receives an analog input signal in different non-overlapping durations of a clock signal and generates a corresponding analog output signal. At least one of the converters is coupled with at least two DACs, and each converter is configured to receive the corresponding analog output signals and perform conversion operation to generate digital signals in non-overlapping durations of the clock signal, respectively. The durations for performing conversion operation of at least two of the converters overlap partially.

Abstract: A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), an amplifier, and a conversion circuit. The multiple DACs function in a pipelined manner such that each DAC receives an analog input signal in different cycles of a clock signal and generates a corresponding analog output signal. The amplifier amplifies each analog output signal to generate a corresponding amplified analog signal in different cycles of the clock signal. The conversion circuit successively approximates each analog output signal to generate multiple digital signals. Thus, a digital output signal of the pipeline ADC is generated based on the corresponding amplified analog signal and at least one of the multiple digital signals. The pipeline ADC utilizes one cycle for performing each of sampling, conversion, and amplification operations, which results into low power consumption by the pipeline ADC.

Abstract: A sub-ranging analog-to-digital converter (ADC) converts an analog input signal to a digital output signal. The sub-ranging ADC includes a coarse ADC, a fine ADC, and an error correction circuit (ECC). The fine ADC includes at least three digital-to-analog converters (DACs) that are connected in a pipeline architecture. The coarse and fine ADCs receive the analog input signal in a first half cycle of a clock signal. The coarse ADC converts the analog input signal to a first digital signal in a second half cycle of the clock signal. At least one of the first through third DACs converts the analog input signal to a second digital signal in a full cycle of the clock signal. The ECC receives the first and second digital signals and generates the digital output signal.

Abstract: A preamplifier circuit includes a first transconductor and a floating transconductor. The first transconductor receives a differential voltage from a sample-and-hold circuit and drives the floating transconductor. The first and floating transconductors output amplified versions of the differential voltage that are not affected by capacitive division, which makes the preamplifier circuit fast. The preamplifier circuit also has a low input capacitance because the floating transconductor is not connected to any external circuitry.

Abstract: A sample-and-hold circuit is broken down into multiple parallel modules, and an output switch, where each module includes a switch and a capacitor. Each of the switches in the modules and the output switch are controlled by different phases of a clock signal. The sample-and-hold circuit receives an input signal and operates in sample and hold modes to generate a sampled output signal.

Abstract: The present invention provides a high-voltage tolerant input buffer circuit including a first NMOS transistor having its source terminal connected to the input pin, its gate terminal connected to a first reference voltage and its drain terminal connected to a first output terminal; a second NMOS transistor having its gate terminal connected to said first reference voltage and its source terminal connected to said first output terminal; a first PMOS transistor having its gate terminal connected to the drain terminal of said second NMOS transistor, its drain terminal connected to a second reference voltage lower than said first reference voltage and its source terminal connected to a second output terminal; a second PMOS transistor having its drain terminal connected to the drain terminal of said second NMOS transistor, its source terminal connected to said second output terminal, and its gate terminal connected to a control voltage; and a third PMOS transistor having its drain terminal connected to said second

Abstract: A master latch implemented to receive feedback from a slave latch on a different input terminal than a input terminal on which data bits are received. Due to such receiving, the number of transistors/area and/or power consumption requirements (efficiently) may be minimized in implementing a flip-flop. The feedback path may be implemented using a single pass-gate, further enhancing the efficiency of implementation. In addition, clock enable/disable signals may be generated efficiently taking into account an externally received flip-flop disable signal and absence of transitions in the data input bits. When the flip-flop is implemented to support ATPG type sequential scanning testing, a multiplexor may be implemented efficiently to select either the data bits or scan bits.

Abstract: A master latch implemented to receive feedback from a slave latch on a different input terminal than a input terminal on which data bits are received. Due to such receiving, the number of transistors/area and/or power consumption requirements (efficiently) may be minimized in implementing a flip-flop. The feedback path may be implemented using a single pass-gate, further enhancing the efficiency of implementation. In addition, clock enable/disable signals may be generated efficiently taking into account an externally received flip-flop disable signal and absence of transitions in the data input bits. When the flip-flop is implemented to support ATPG type sequential scanning testing, a multiplexor may be implemented efficiently to select either the data bits or scan bits.