Abstract: A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.

Abstract: A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.

Abstract: A clock synchronization circuit includes a multi-phase clock generator to generate a plurality of delayed clocks, each delayed clock having a unique delay with regard to a source clock. The clock synchronization circuit further includes a selection circuit that selects one of the delayed clocks according to a phase error to form a local clock driven into a local clock path and received at the clock synchronization circuit as a received local clock. The selection circuit determines the phase error by comparing the received local clock to a reference clock.