Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, including: a non-volatile memory array, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to transfer the user data with the interface circuit or the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree to access the user data; and wherein: the interface circuit, connected to a device coupling structure, configured to receive the key value transfer command; and the device processor is configured to address the non-volatile memory array, the volatile memory, or both concurrently based on a key value transfer.

Abstract: A storage device, such as a NAND flash device, includes a controller that assigns host read commands to a high priority queue and all other I/O commands including host write commands to a low priority queue. The controller executes any commands in the high priority queue before executing commands in the low priority queue. Block write commands are broken into page write commands that are added to the low priority queue, thereby enabling any host read commands to be interleaved with execution of the page write commands, rather than waiting for completion of a block write command. Coherency between overlapping commands is performed by a host device coupled to the controller such that no checking of coherency is performed by the SSD controller.

Abstract: A storage device, such as a NAND flash device, avoids the need for garbage collection. An application executing on a host system tracks data objects that are marked as invalid and maintains an association between data objects and logical blocks, each logical block corresponding to a physical block of memory in the NAND flash device. Upon determining that the logical block contains no valid objects, the application instructs an SSD to trim the physical block of memory corresponding to the logical block. The application also aggregates write commands until a full block of data is ready to be written, at which point the application transmits a write command to the SSD.

Abstract: An electronic system includes: a storage device configured to store a descriptor, including a key and a value, having multiple versions linked on the storage device; a storage interface, coupled to the storage device, configured to provide an entry having a location; and retrieve the descriptor, including the key and the value, based on the entry having the location for selecting one of the versions of the descriptor.

Abstract: A storage device, such as a NAND flash device, includes a controller that maintains a temperature for a plurality of data blocks, the temperature calculated according to a function that increases with a number of valid data objects in the block and recency with which the valid data objects have been accessed. Blocks with the lowest temperature are selected for garbage collection. Recency for a block is determined based on a number of valid data objects stored in the block that are referenced in a hot list of a LRU list. During garbage collection, data objects that are least recently used are invalidated to reduce write amplification.

Abstract: A storage device, such as a NAND flash device, avoids the need for garbage collection. An application executing on a host system tracks data objects that are marked as invalid and maintains an association between data objects and logical blocks, each logical block corresponding to a physical block of memory in the NAND flash device. Upon determining that the logical block contains no valid objects, the application instructs an SSD to trim the physical block of memory corresponding to the logical block. The application also aggregates write commands until a full block of data is ready to be written, at which point the application transmits a write command to the SSD.

Abstract: A storage device, such as a NAND flash device, includes a controller that maintains a temperature for a plurality of data blocks, the temperature calculated according to a function that increases with a number of valid data objects in the block and recency with which the valid data objects have been accessed. Blocks with the lowest temperature are selected for garbage collection. Recency for a block is determined based on a number of valid data objects stored in the block that are referenced in a hot list of a LRU list. During garbage collection, data objects that are least recently used are invalidated to reduce write amplification.

Abstract: A storage device, such as a NAND flash device, includes a controller that assigns host read commands to a high priority queue and all other I/O commands including host write commands to a low priority queue. The controller executes any commands in the high priority queue before executing commands in the low priority queue. Block write commands are broken into page write commands that are added to the low priority queue, thereby enabling any host read commands to be interleaved with execution of the page write commands, rather than waiting for completion of a block write command. Coherency between overlapping commands is performed by a host device coupled to the controller such that no checking of coherency is performed by the SSD controller.

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, including: a non-volatile memory array, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to transfer the user data with the interface circuit or the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree to access the user data; and wherein: the interface circuit, connected to a device coupling structure, configured to receive the key value transfer command; and the device processor is configured to address the non-volatile memory array, the volatile memory, or both concurrently based on a key value transfer.

Abstract: An electronic system includes: a storage device configured to store a descriptor, including a key and a value, having multiple versions linked on the storage device; a storage interface, coupled to the storage device, configured to provide an entry having a location; and retrieve the descriptor, including the key and the value, based on the entry having the location for selecting one of the versions of the descriptor.