Abstract: A system may include multiple electrical components. One electrical component such as an imaging sub-system may be communicatively coupled to another electrical component such as control circuitry for the system. The imaging-subsystem may include transmitter circuitry. The transmitter circuitry can include driver circuitry configured to provide the transmitter circuitry output using a multi-level signaling scheme. To generate the control signals for the driver circuitry, pre-driver combinational logic may precede the serializer circuitry and be coupled to the word data latch circuitry. In such a manner, the generated control signals for different portions of the driver circuitry can be better synchronized with one another, thereby helping improve data EYE margin in the multi-level signal scheme.

Abstract: A system may include multiple electrical components. One electrical component such as an imaging sub-system may be communicatively coupled to another electrical component such as control circuitry for the system. The imaging-subsystem may include transmitter circuitry. The transmitter circuitry can include driver circuitry configured to provide the transmitter circuitry output using a multi-level signaling scheme. To generate the control signals for the driver circuitry, pre-driver combinational logic may precede the serializer circuitry and be coupled to the word data latch circuitry. In such a manner, the generated control signals for different portions of the driver circuitry can be better synchronized with one another, thereby helping improve data EYE margin in the multi-level signal scheme.

Abstract: Devices include an array of memory cells arranged in rows and columns. Wordlines are connected to the memory cells, and each of the wordlines is connected to a distinct row of the array of the memory cells. A wordline driver circuit is connected to a near end of the wordlines. The wordline driver circuit outputs a wordline select signal. Also, a feedback circuit is connected to a far end of each of the wordlines, opposite the near end of the wordlines. The feedback circuit includes first transistors (gated by the internal clock signal and the wordline select signal) electrically connecting a relatively lower voltage source to the far end of the wordlines; and second transistors (also gated by the internal clock signal and the wordline select signal) electrically connecting a relatively higher voltage source to the far end of the wordlines.

Abstract: A reference circuit can include a reference section that provides a reference value for other circuits of an integrated circuit and can be enabled and disabled in response to an enable signal. The reference circuit can include at least a first node, draw a reference current in the enabled mode, and draw essentially no current in the disabled mode. A pulse start-up section can provides a low impedance path between the first node and a first potential for a predetermined duration in response to the reference circuit being enabled. A continuous start-up section can provide a low impedance path between the first node and the first potential based on a logic state of an enable signal.

Abstract: A reference circuit can include a reference section that provides a reference value for other circuits of an integrated circuit and can be enabled and disabled in response to an enable signal. The reference circuit can include at least a first node, draw a reference current in the enabled mode, and draw essentially no current in the disabled mode. A pulse start-up section can provides a low impedance path between the first node and a first potential for a predetermined duration in response to the reference circuit being enabled. A continuous start-up section can provide a low impedance path between the first node and the first potential based on a logic state of an enable signal.