Abstract: Methods and apparatuses for variable length decoding using multiple look-up tables simultaneously. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a string of bits; generating a plurality of indices using a plurality of segments of bits in the string of bits; looking up simultaneously a plurality of entries from a plurality of look-up tables using the plurality of indices; and combining the plurality of entries into a first result. The above operations are performed in response to the microprocessor receiving the single instruction.

Abstract: Methods and apparatuses for computing an absolute difference of two vectors of numbers. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a first plurality of numbers and a second plurality of numbers; and generating simultaneously a third plurality of numbers, each of which is an absolute difference between a number in the first plurality of numbers and a number in the second plurality of numbers. The above operations are performed in response to the microprocessor receiving the single instruction.

Abstract: Methods and apparatuses for performing vector table look-up using multiple look-up tables. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a plurality of numbers; partitioning look-up memory into a plurality of look-up tables; looking up simultaneously a plurality of elements from the plurality of look-up tables. Each of the plurality of elements is in one of the plurality of look-up tables and is pointed to by one of the plurality of numbers. The above operations are performed in response to the microprocessor receiving the single instruction.

Abstract: Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling the host memory comprising DRAM memory, the memory controller coupled to the chip interconnect, a scalar processing unit coupled the chip interconnect wherein the scalar processing unit is capable of executing instructions to perform scalar data processing, a vector processing unit coupled the chip interconnect wherein the vector processing unit is capable of executing instructions to perform vector data processing, and an input/output (I/O) interface coupled to the chip interconnect wherein the I/O interface receives/transmits data from/to the scalar and/or vector processing units.

Abstract: Methods and apparatuses for dispatching instructions executed by at least one functional unit of a data processor, each one of the instructions having a corresponding priority number, in a data processing system having at least one host processor with host processor cache and host memory are described herein. In one aspect of the invention, an exemplary method includes receiving a next instruction from an instruction stream, examining a current instruction group to determine if the current instruction group is completed, adding the next instruction to the current instruction group if the current instruction group is not completed, and dispatching the current instruction group if the current instruction group is completed.

Abstract: Methods and apparatuses for performing simultaneous table look-up using multiple look-up tables. In one aspect of the invention, an execution unit in a microprocessor includes: look-up memory and a first circuit coupled to the look-up memory. In response to the microprocessor receiving a first instruction, the first circuit partitions the look-up memory into a first plurality of look-up tables. In response to the microprocessor receiving a second instruction, the first circuit partitions the look-up memory into a second plurality of look-up tables; and the second plurality of look-up tables simultaneously look up a plurality of entries.

Abstract: An apparatus, in a data processing system having at least one host processor with host processor cache and host memory, includes a chip interconnect, a cache coherent interface coupled to the chip interconnect wherein the cache coherent interface provides cache coherent access, a cache non-coherent interface coupled to the chip interconnect wherein the cache non-coherent interface provides cache non-coherent access to the host memory, and a compute engine coupled to the chip interconnect and coupled to the cache coherent interface and coupled to cache non-coherent interface wherein the compute engine issues a memory access request. Other methods and apparatuses are also described.

Abstract: At least one chip of a chipset in a computer system having at least one host processor and a host memory are described herein. In one aspect of the invention, an exemplary chip includes an interconnect, a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access, a host interface coupled to the interconnect, the host interface providing access to the host processor, and a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media.

Abstract: Methods and apparatuses for mapping a logical address to a physical address, in a data processing system having at least one host processor with host processor cache and host memory. In one aspect of the invention, an exemplary method includes translating a memory access request from logical addresses to physical addresses through a memory mapping mechanism, determining whether the physical address is configured for cache coherent access, if so, transmitting the request to cache coherent interface, and otherwise, transmitting the request to cache non-coherent interface. Other methods and apparatuses are also described.

Abstract: Methods and apparatuses for converting color components in one space to those in another space. In one aspect of the invention, a method for vector conversion including: loading a first vector of components into a vector register; generating a first vector of indices in a vector register, each index of the first vector of indices being one of the first vector of components, at least one component in the first vector of components being replicated as a plurality of duplicated indices in the first vector of indices; looking up simultaneously a first vector of data items from a plurality of look up tables using the first vector of indices; and summing up at least one subset of the first vector of data items into at least one component of a second vector of components.

Abstract: Methods and apparatuses for decoding a compressed video stream. In one aspect of the invention, a method to decode a variable length encoded bit stream includes: concurrently processing first data obtained from variable length decoding a first code word in a register while variable length decoding a second code word in the register. In one example, processing the first data includes: looking up an inverse zigzag index; computing an Inverse Direct Cosine Transformation (IDCT) coefficient; storing the IDCT coefficient in a buffer in a transposed inverse zigzag order; and branching conditionally based on a condition encountered in variable length decoding the first code word.