Abstract: Systems, methodologies, media, and other embodiments associated with acquiring instruction addresses associated with performance monitoring events are described. One exemplary system embodiment includes logic for recording instruction and state data associated with events countable by performance monitoring logic associated with a pipelined processor. The exemplary system embodiment may also include logic for traversing the instruction and state data on a cycle count basis. The exemplary system may also include logic for traversing the instruction and state data on a retirement count basis.

Abstract: A branch target structure predicts a branch target address for an instruction flow. To conserve space, only a portion of the branch target address is stored. The branch target address is reconstructed assuming that an unspecified portion of a current branch instruction address matches corresponding bits of the branch target address. A comparator determines if the unspecified portion of the current branch instruction address matches corresponding bits of the branch target address. If the unspecified portion of the current branch instruction address does not match the corresponding bits of the branch target address, update of the branch target structure is inhibited. Otherwise update allowed.

Abstract: A branch target structure predicts a branch target address for an instruction flow. To conserve space, only a portion of the branch target address is stored. The branch target address is reconstructed assuming that an unspecified portion of a current instruction address matches corresponding bits of the branch target address. A comparator determines if the unspecified portion of the current instruction address matches corresponding bits of the branch target address. If the unspecified portion of the address does not match the corresponding bits of the branch instruction address, update of the branch target structure is inhibited. Otherwise update allowed.