Patents by Inventor Susmita Karmakar
Susmita Karmakar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11586553Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.Type: GrantFiled: September 13, 2021Date of Patent: February 21, 2023Assignee: Integrated Silicon Solution, (Cayman) Inc.Inventors: Neal Berger, Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim
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Patent number: 11580014Abstract: A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.Type: GrantFiled: September 13, 2021Date of Patent: February 14, 2023Assignee: Integrated Silicon Solution, (Cayman) Inc.Inventors: Neal Berger, Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim
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Patent number: 11423965Abstract: A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.Type: GrantFiled: March 26, 2020Date of Patent: August 23, 2022Assignee: Integrated Silicon Solution, (Cayman) Inc.Inventors: Neal Berger, Susmita Karmakar, Benjamin Louie
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Publication number: 20220107900Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.Type: ApplicationFiled: September 13, 2021Publication date: April 7, 2022Inventors: Neal BERGER, Susmita KARMAKAR, TaeJin PYON, Kuk-Hwan KIM
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Publication number: 20220107888Abstract: A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.Type: ApplicationFiled: September 13, 2021Publication date: April 7, 2022Inventors: Neal BERGER, Susmita KARMAKAR, TaeJin PYON, Kuk-Hwan KIM
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Patent number: 11119910Abstract: A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.Type: GrantFiled: October 10, 2019Date of Patent: September 14, 2021Assignee: SPIN MEMORY, INC.Inventors: Neal Berger, Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim
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Patent number: 11119936Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.Type: GrantFiled: October 10, 2019Date of Patent: September 14, 2021Assignee: Spin Memory, Inc.Inventors: Neal Berger, Susmita Karmakar, TaeJin Pyon, Kuk-Hwan Kim
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Patent number: 11048633Abstract: A method of writing data into a memory device comprising utilizing a pipeline to process write operations of a first plurality of data words addressed to a plurality of memory banks, wherein each of the plurality of memory banks is associated with a counter. The method also comprises writing a second plurality of data words and associated memory addresses into an error buffer, wherein the error buffer is associated with the plurality of memory banks and wherein further each data word of the second plurality of data words is either awaiting write verification associated with a bank from the plurality of memory banks or is to be re-written into a bank from the plurality of memory banks. Further, the method comprises maintaining a count in each of the plurality of counters for a respective number of entries in the error buffer corresponding to a respective memory bank.Type: GrantFiled: October 10, 2019Date of Patent: June 29, 2021Assignee: Spin Memory, Inc.Inventors: Susmita Karmakar, Neal Berger
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Patent number: 10930332Abstract: A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.Type: GrantFiled: July 23, 2019Date of Patent: February 23, 2021Assignee: Spin Memory, Inc.Inventors: Susmita Karmakar, Neal Berger, Mourad El Baraji, Benjamin Louie
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Patent number: 10803949Abstract: A clocked driver circuit can include a master-slave level shifter latch and a driver. The master-slave level shifter latch can be configured to receive an input signal upon a first state of a clock signal, latch the input signal upon a second state of the clock signal and generate a level shifted output signal corresponding to the latched input signal. The driver can be configured to receive the level shifted output signal from the master-slave level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.Type: GrantFiled: March 7, 2019Date of Patent: October 13, 2020Assignee: Spin Memory, Inc.Inventors: Neal Berger, Susmita Karmakar, Benjamin Louie
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Publication number: 20200286561Abstract: A clocked driver circuit can include a master-slave level shifter latch and a driver. The master-slave level shifter latch can be configured to receive an input signal upon a first state of a clock signal, latch the input signal upon a second state of the clock signal and generate a level shifted output signal corresponding to the latched input signal. The driver can be configured to receive the level shifted output signal from the master-slave level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.Type: ApplicationFiled: March 7, 2019Publication date: September 10, 2020Inventors: Neal BERGER, Susmita KARMAKAR, Benjamin LOUIE
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Publication number: 20200227102Abstract: A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventors: Neal BERGER, Susmita KARMAKAR, Benjamin LOUIE
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Patent number: 10699761Abstract: A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.Type: GrantFiled: September 18, 2018Date of Patent: June 30, 2020Assignee: Spin Memory, Inc.Inventors: Neal Berger, Susmita Karmakar, Benjamin Louie
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Publication number: 20200117592Abstract: A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.Type: ApplicationFiled: October 10, 2019Publication date: April 16, 2020Inventors: Neal BERGER, Susmita KARMAKAR, TaeJin PYON, Kuk-Hwan KIM
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Publication number: 20200117610Abstract: A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.Type: ApplicationFiled: October 10, 2019Publication date: April 16, 2020Inventors: Neal BERGER, Susmita KARMAKAR, TaeJin PYON, Kuk-Hwan KIM
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Publication number: 20200090721Abstract: A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.Type: ApplicationFiled: September 18, 2018Publication date: March 19, 2020Inventors: Neal BERGER, Susmita KARMAKAR, Benjamin LOUIE
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Publication number: 20200042451Abstract: A method of writing data into a memory device comprising utilizing a pipeline to process write operations of a first plurality of data words addressed to a plurality of memory banks, wherein each of the plurality of memory banks is associated with a counter. The method also comprises writing a second plurality of data words and associated memory addresses into an error buffer, wherein the error buffer is associated with the plurality of memory banks and wherein further each data word of the second plurality of data words is either awaiting write verification associated with a bank from the plurality of memory banks or is to be re-written into a bank from the plurality of memory banks. Further, the method comprises maintaining a count in each of the plurality of counters for a respective number of entries in the error buffer corresponding to a respective memory bank.Type: ApplicationFiled: October 10, 2019Publication date: February 6, 2020Inventors: Susmita KARMAKAR, Neal BERGER
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Publication number: 20190348097Abstract: A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.Type: ApplicationFiled: July 23, 2019Publication date: November 14, 2019Inventors: Susmita KARMAKAR, Neal BERGER, Mourad EL BARAJI, Benjamin LOUIE
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Patent number: 10360962Abstract: A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.Type: GrantFiled: December 28, 2017Date of Patent: July 23, 2019Assignee: Spin Memory, Inc.Inventors: Susmita Karmakar, Neal Berger, Mourad El Baraji, Benjamin Louie
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Publication number: 20190206467Abstract: A device includes an array of memory cells, input/output lines coupled to the memory cells, and sense amplifiers coupled to the input/output lines. Each sense amplifier is associated with a respective input/output line. The device also includes trim circuits. Each trim circuit is associated with and coupled to a respective sense amplifier. Each sense amplifier receives a respective reference voltage that allows the sense amplifier to sense a bit value of an addressed memory cell. Each trim circuit is operable for compensating for variations in the reference voltage used by the respective sense amplifier.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Inventors: Susmita KARMAKAR, Neal BERGER, Mourad EL BARAJI, Benjamin LOUIE