Patents by Inventor Susumu Akamatsu
Susumu Akamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8796779Abstract: A first MIS transistor and a second MIS transistor of the same conductivity type are formed on an identical semiconductor substrate. An interface layer included in a gate insulating film of the first MIS transistor has a thickness larger than that of an interface layer included in a gate insulating film of the second MIS transistor.Type: GrantFiled: October 31, 2012Date of Patent: August 5, 2014Assignee: Panasonic CorporationInventors: Satoru Ito, Yoshiya Moriyama, Hiroshi Ohkawa, Susumu Akamatsu
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Patent number: 8779524Abstract: A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1<0.5s.Type: GrantFiled: July 20, 2012Date of Patent: July 15, 2014Assignee: Panasonic CorporationInventors: Yoshiya Moriyama, Hiromasa Fujimoto, Satoru Itou, Susumu Akamatsu, Hiroshi Ohkawa
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Patent number: 8729641Abstract: A semiconductor device includes a first, second, and third MIS transistors of a first conductivity type respectively including a first, second, and third gate electrodes on a first, second, and third active regions of a semiconductor substrate with a first, second, and third gate insulating films interposed therebetween. The first gate insulating film is formed of a first silicon oxide film and a first high-k insulating film on the first silicon oxide film. The second gate insulating film is formed of a second silicon oxide film and a second high-k insulating film on the second silicon oxide film. The third gate insulating film is formed of a third silicon oxide film and a third high-k insulating film on the third silicon oxide film. The second silicon oxide film has a same thickness as the first silicon oxide film, and a greater thickness than the third silicon oxide film.Type: GrantFiled: November 10, 2011Date of Patent: May 20, 2014Assignee: Panasonic CorporationInventor: Susumu Akamatsu
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Patent number: 8604554Abstract: A semiconductor device includes a first and a second MIS transistor. The first and second MIS transistors include a first and a second gate electrode formed on a first and a second active region with a first and a second gate insulating film being formed therebetween, first and second sidewalls including a first and a second inner sidewall formed on side surfaces of the first and second gate electrodes and having an L-shaped cross-section, and first and second source/drain regions formed in the first and second active regions laterally outside the first and second sidewalls. The first source/drain regions include a silicon compound layer formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region. A width of the first inner sidewall is smaller than a width of the second inner sidewall.Type: GrantFiled: February 17, 2012Date of Patent: December 10, 2013Assignee: Panasonic CorporationInventors: Satoru Itou, Hiromasa Fujimoto, Susumu Akamatsu, Toshie Kutsunai
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Publication number: 20120280328Abstract: A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1<0.5 s.Type: ApplicationFiled: July 20, 2012Publication date: November 8, 2012Applicant: Panasonic CorporationInventors: Yoshiya MORIYAMA, Hiromasa FUJIMOTO, Satoru ITOU, Susumu AKAMATSU, Hiroshi OHKAWA
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Publication number: 20120146154Abstract: A semiconductor device includes a first and a second MIS transistor. The first and second MIS transistors include a first and a second gate electrode formed on a first and a second active region with a first and a second gate insulating film being formed therebetween, first and second sidewalls including a first and a second inner sidewall formed on side surfaces of the first and second gate electrodes and having an L-shaped cross-section, and first and second source/drain regions formed in the first and second active regions laterally outside the first and second sidewalls. The first source/drain regions include a silicon compound layer formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region. A width of the first inner sidewall is smaller than a width of the second inner sidewall.Type: ApplicationFiled: February 17, 2012Publication date: June 14, 2012Applicant: PANASONIC CORPORATIONInventors: SATORU ITOU, HIROMASA FUJIMOTO, SUSUMU AKAMATSU, TOSHIE KUTSUNAI
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Publication number: 20120056271Abstract: A semiconductor device includes a first, second, and third MIS transistors of a first conductivity type respectively including a first, second, and third gate electrodes on a first, second, and third active regions of a semiconductor substrate with a first, second, and third gate insulating films interposed therebetween. The first gate insulating film is formed of a first silicon oxide film and a first high-k insulating film on the first silicon oxide film. The second gate insulating film is formed of a second silicon oxide film and a second high-k insulating film on the second silicon oxide film. The third gate insulating film is formed of a third silicon oxide film and a third high-k insulating film on the third silicon oxide film. The second silicon oxide film has a same thickness as the first silicon oxide film, and a greater thickness than the third silicon oxide film.Type: ApplicationFiled: November 10, 2011Publication date: March 8, 2012Applicant: Panasonic CorporationInventor: Susumu AKAMATSU
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Patent number: 7999331Abstract: In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.Type: GrantFiled: December 6, 2010Date of Patent: August 16, 2011Assignee: Panasonic CorporationInventors: Susumu Akamatsu, Masafumi Tsutsui, Yoshinori Takami
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Patent number: 7964917Abstract: A semiconductor device includes a plurality of first MIS transistors and a plurality of second MIS transistors formed on a semiconductor substrate and a liner insulating film applying stress along the gate length direction. Each of the first MIS transistors includes first L-shaped sidewalls each having an L-shaped cross-sectional shape, and each of the second MIS transistors includes second L-shaped sidewalls each having an L-shaped cross-sectional shape and outer sidewalls. The minimum thickness of a part of the liner insulating film located on each of second source/drain regions of the second MIS transistor is larger than the minimum thickness of a part thereof located on each of first source/drain regions of the first MIS transistor.Type: GrantFiled: October 18, 2007Date of Patent: June 21, 2011Assignee: Panasonic CorporationInventor: Susumu Akamatsu
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Publication number: 20110073954Abstract: In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.Type: ApplicationFiled: December 6, 2010Publication date: March 31, 2011Applicant: PANASONIC CORPORATIONInventors: Susumu AKAMATSU, Masafumi Tsutsui, Yoshinori Takami
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Patent number: 7867840Abstract: In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.Type: GrantFiled: June 8, 2010Date of Patent: January 11, 2011Assignee: Panasonic CorporationInventors: Susumu Akamatsu, Masafumi Tsutsui, Yoshinori Takami
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Patent number: 7829924Abstract: A trench isolation surrounding the lateral sides of an active region of a P-channel MIS transistor PTr and a trench isolation surrounding the lateral sides of an active region of an N-channel MIS transistor NTr have different film qualities.Type: GrantFiled: October 11, 2006Date of Patent: November 9, 2010Assignee: Panasonic CorporationInventor: Susumu Akamatsu
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Publication number: 20100248438Abstract: In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.Type: ApplicationFiled: June 8, 2010Publication date: September 30, 2010Applicant: Panasonic CorporationInventors: Susumu AKAMATSU, Masafumi Tsutsui, Yoshinori Takami
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Patent number: 7772655Abstract: In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.Type: GrantFiled: June 5, 2007Date of Patent: August 10, 2010Assignee: Panasonic CorporationInventors: Susumu Akamatsu, Masafumi Tsutsui, Yoshinori Takami
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Patent number: 7737510Abstract: A gate insulating film and a gate electrode are formed on an active region of a semiconductor substrate. A sidewall forming an L shape in cross section is formed on the sides of the gate electrode. Source/drain regions are formed in regions of the semiconductor substrate located outside an area covering the gate electrode and the sidewall. A stress-applying stress liner film is formed to cover the gate electrode and the sidewall.Type: GrantFiled: October 11, 2006Date of Patent: June 15, 2010Assignee: Panasonic CorporationInventor: Susumu Akamatsu
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Publication number: 20080173954Abstract: A semiconductor device includes a plurality of first MIS transistors and a plurality of second MIS transistors formed on a semiconductor substrate and a liner insulating film applying stress along the gate length direction. Each of the first MIS transistors includes first L-shaped sidewalls each having an L-shaped cross-sectional shape, and each of the second MIS transistors includes second L-shaped sidewalls each having an L-shaped cross-sectional shape and outer sidewalls. The minimum thickness of a part of the liner insulating film located on each of second source/drain regions of the second MIS transistor is larger than the minimum thickness of a part thereof located on each of first source/drain regions of the first MIS transistor.Type: ApplicationFiled: October 18, 2007Publication date: July 24, 2008Inventor: Susumu Akamatsu
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Publication number: 20080036014Abstract: In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an impurity concentration peak at a position close to a surface of the substrate are formed. Then, extension regions are formed in the first section, the second section and the third section. After that, the substrate is thermally treated to eliminate defects produced in the extension regions. Then, using gate electrodes and side-wall spacers as a mask, source/drain regions are formed in the first section, the second section and the third section.Type: ApplicationFiled: June 5, 2007Publication date: February 14, 2008Inventors: Susumu Akamatsu, Masafumi Tsutsui, Yoshinori Takami
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Patent number: 7288807Abstract: After a capacitor forming portion is formed on a semiconductor substrate by patterning an insulating film and a silicon film, a sidewall insulating film is formed on each of the side surfaces of the capacitor forming portion. Then, the insulating film is selectively removed such that the silicon film is exposed in a depressed portion surrounded by the sidewall insulating film. Subsequently, a first metal film is deposited and then a thermal process is performed to change the silicon film into a first metal film. Thereafter, an insulating film and a second metal film are buried in the depressed portion. The insulating film composes the capacitor insulating film of a capacitor element. The first metal silicide film and the second metal film compose the lower and upper electrodes of the capacitor element, respectively.Type: GrantFiled: September 11, 2006Date of Patent: October 30, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Susumu Akamatsu
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Publication number: 20070173025Abstract: First and second gate portions each made of a gate insulating film, a silicon film, and a protective film are formed on a semiconductor substrate. Then, a first sidewall insulating film is formed on each of the side surfaces of the first and second gate portions. Subsequently, the protective film is removed such that the silicon film is exposed. A thermal process is performed with respect to a Ni film deposited on the silicon film to convert the silicon film to a NiSi film and then an insulating film is formed on the NiSi film. Thereafter, a Ni film is deposited on the NiSi film and a thermal process is performed to convert the NiSi film to a Ni3Si film.Type: ApplicationFiled: October 2, 2006Publication date: July 26, 2007Inventor: Susumu Akamatsu
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Publication number: 20070170548Abstract: After a capacitor forming portion is formed on a semiconductor substrate by patterning an insulating film and a silicon film, a sidewall insulating film is formed on each of the side surfaces of the capacitor forming portion. Then, the insulating film is selectively removed such that the silicon film is exposed in a depressed portion surrounded by the sidewall insulating film. Subsequently, a first metal film is deposited and then a thermal process is performed to change the silicon film into a first metal film. Thereafter, an insulating film and a second metal film are buried in the depressed portion. The insulating film composes the capacitor insulating film of a capacitor element. The first metal silicide film and the second metal film compose the lower and upper electrodes of the capacitor element, respectively.Type: ApplicationFiled: September 11, 2006Publication date: July 26, 2007Inventor: Susumu Akamatsu