Patents by Inventor Susumu HATAKENAKA
Susumu HATAKENAKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11107677Abstract: A SiC varied-growth-rate layer (2) is formed on a SiC bulk substrate (1) while increasing a growth speed from an initial growth speed of 2.0 ?m/h or less. A speed change rate of the SiC varied-growth-rate layer (2) is 720 ?m/h2 or less. A molar flow ratio of nitrogen to carbon when growth of the SiC varied-growth-rate layer (2) starts is 2.4 or less.Type: GrantFiled: May 23, 2018Date of Patent: August 31, 2021Assignee: Mitsubishi Electric CorporationInventor: Susumu Hatakenaka
-
Publication number: 20210125824Abstract: A SiC varied-growth-rate layer (2) is formed on a SiC bulk substrate (1) while increasing a growth speed from an initial growth speed of 2.0 ?m/h or less. A speed change rate of the SiC varied-growth-rate layer (2) is 720 ?m/h2 or less. A molar flow ratio of nitrogen to carbon when growth of the SiC varied-growth-rate layer (2) starts is 2.4 or less.Type: ApplicationFiled: May 23, 2018Publication date: April 29, 2021Applicant: Mitsubishi Electric CorporationInventor: Susumu HATAKENAKA
-
Patent number: 10199218Abstract: A Ga source gas and a nitrogen source gas are supplied to form a GaN channel layer on a semiconductor substrate. Next, a temperature is lowered while supplying at least the nitrogen source gas. Next, the Ga source gas is not supplied and an Al source gas and the nitrogen source gas are supplied. Next, the temperature is raised while not supplying the Al source gas and the Ga source gas and supplying the nitrogen source gas. Next, the Al source gas and the nitrogen source gas are supplied and at least one of the Ga source gas and an In source gas is supplied to form a AlxGayInzN barrier layer (x+y+z=1, x>0, y?0, z?0, y+z>0).Type: GrantFiled: July 24, 2017Date of Patent: February 5, 2019Assignee: Mitsubishi Electric CorporationInventors: Atsushi Era, Susumu Hatakenaka
-
Publication number: 20180166271Abstract: A Ga source gas and a nitrogen source gas are supplied to form a GaN channel layer on a semiconductor substrate. Next, a temperature is lowered while supplying at least the nitrogen source gas. Next, the Ga source gas is not supplied and an Al source gas and the nitrogen source gas are supplied. Next, the temperature is raised while not supplying the Al source gas and the Ga source gas and supplying the nitrogen source gas. Next, the Al source gas and the nitrogen source gas are supplied and at least one of the Ga source gas and an In source gas is supplied to form a AlxGayInzN barrier layer (x+y+z=1, x>0, y?0, z?0, y+z>0).Type: ApplicationFiled: July 24, 2017Publication date: June 14, 2018Applicant: Mitsubishi Electric CorporationInventors: Atsushi ERA, Susumu HATAKENAKA
-
Publication number: 20170301761Abstract: A semiconductor device includes: a substrate; a first GaN layer on the substrate and containing carbon; a second GaN layer on the first GaN layer and containing transition metal and carbon; a third GaN layer on the second GaN layer and containing transition metal and carbon; and an electron supply layer on the third GaN layer and having a larger band gap than GaN. A transition metal concentration of the third GaN layer gradually decreases from that of the second GaN layer from the second GaN layer toward the electron supply layer and is higher than 1×1015 cm3 at a position of 100 nm deep from a bottom end of the electron supply layer. A top end of the second GaN layer is deeper than 800 nm from the bottom end. A carbon concentration of the third GaN layer is lower than those of the first and second GaN layers.Type: ApplicationFiled: July 3, 2017Publication date: October 19, 2017Applicant: Mitsubishi Electric CorporationInventors: Atsushi ERA, Susumu HATAKENAKA
-
Patent number: 9793363Abstract: A semiconductor device includes: a substrate; a first GaN layer on the substrate and containing carbon; a second GaN layer on the first GaN layer and containing transition metal and carbon; a third GaN layer on the second GaN layer and containing transition metal and carbon; and an electron supply layer on the third GaN layer and having a larger band gap than GaN. A transition metal concentration of the third GaN layer gradually decreases from that of the second GaN layer from the second GaN layer toward the electron supply layer and is higher than 1×1015 cm?3 at a position of 100 nm deep from a bottom end of the electron supply layer. A top end of the second GaN layer is deeper than 800 nm from the bottom end. A carbon concentration of the third GaN layer is lower than those of the first and second GaN layers.Type: GrantFiled: July 3, 2017Date of Patent: October 17, 2017Assignee: Mitsubishi Electric CorporationInventors: Atsushi Era, Susumu Hatakenaka
-
Patent number: 9728611Abstract: A semiconductor device includes: a substrate; a first GaN layer on the substrate and containing carbon; a second GaN layer on the first GaN layer and containing transition metal and carbon; a third GaN layer on the second GaN layer and containing transition metal and carbon; and an electron supply layer on the third GaN layer and having a larger band gap than GaN. A transition metal concentration of the third GaN layer gradually decreases from that of the second GaN layer from the second GaN layer toward the electron supply layer and is higher than 1×1015 cm?3 at a position of 100 nm deep from a bottom end of the electron supply layer. A top end of the second GaN layer is deeper than 800 nm from the bottom end. A carbon concentration of the third GaN layer is lower than those of the first and second GaN layers.Type: GrantFiled: May 17, 2016Date of Patent: August 8, 2017Assignee: Mitsubishi Electric CorporationInventors: Atsushi Era, Susumu Hatakenaka
-
Publication number: 20170117404Abstract: A semiconductor device includes: a substrate; a first GaN layer on the substrate and containing carbon; a second GaN layer on the first GaN layer and containing transition metal and carbon; a third GaN layer on the second GaN layer and containing transition metal and carbon; and an electron supply layer on the third GaN layer and having a larger band gap than GaN. A transition metal concentration of the third GaN layer gradually decreases from that of the second GaN layer from the second GaN layer toward the electron supply layer and is higher than 1×1015 cm?3 at a position of 100 nm deep from a bottom end of the electron supply layer. A top end of the second GaN layer is deeper than 800 nm from the bottom end. A carbon concentration of the third GaN layer is lower than those of the first and second GaN layers.Type: ApplicationFiled: May 17, 2016Publication date: April 27, 2017Applicant: Mitsubishi Electric CorporationInventors: Atsushi ERA, Susumu HATAKENAKA
-
Patent number: 9564525Abstract: A compound semiconductor device includes: a substrate; and a buffer layer, a first carrier supply layer, a first spacer layer, a channel layer, a second spacer layer, a second carrier supply layer, and a contact layer provided in order on the substrate, wherein the first carrier supply layer is a uniformly doped layer in which an impurity is uniformly doped, the second carrier supply layer is a planar doped layer in which an impurity is locally doped, and no Al mixed crystal layer having higher resistance values than the first and second spacer layers is provided between the buffer layer and the first spacer layer and between the second spacer layer and the contact layer.Type: GrantFiled: January 7, 2016Date of Patent: February 7, 2017Assignee: Mitsubishi Electric CorporationInventors: Susumu Hatakenaka, Harunaka Yamaguchi
-
Patent number: 9520526Abstract: A manufacturing method of an avalanche photodiode includes: forming a p-type field relaxation layer on a substrate; forming a cap layer on the p-type field relaxation layer; and forming a light absorbing layer on the cap layer, wherein a carbon is doped in the p-type field relaxation layer as a p-type dopant, the p-type field relaxation layer contains Al in a crystal composition, and a temperature-rise process from a growth temperature of the cap layer to a growth temperature of the light absorbing layer is performed in an inactive gas atmosphere without introducing a group V raw material.Type: GrantFiled: August 19, 2015Date of Patent: December 13, 2016Assignee: Mitsubishi Electric CorporationInventors: Harunaka Yamaguchi, Susumu Hatakenaka
-
Publication number: 20160336438Abstract: A compound semiconductor device includes: a substrate; and a buffer layer, a first carrier supply layer, a first spacer layer, a channel layer, a second spacer layer, a second carrier supply layer, and a contact layer provided in order on the substrate, wherein the first carrier supply layer is a uniformly doped layer in which an impurity is uniformly doped, the second carrier supply layer is a planar doped layer in which an impurity is locally doped, and no Al mixed crystal layer having higher resistance values than the first and second spacer layers is provided between the buffer layer and the first spacer layer and between the second spacer layer and the contact layer.Type: ApplicationFiled: January 7, 2016Publication date: November 17, 2016Applicant: Mitsubishi Electric CorporationInventors: Susumu HATAKENAKA, Harunaka YAMAGUCHI
-
Publication number: 20160155888Abstract: A manufacturing method of an avalanche photodiode includes: forming a p-type field relaxation layer on a substrate; forming a cap layer on the p-type field relaxation layer; and forming a light absorbing layer on the cap layer, wherein a carbon is doped in the p-type field relaxation layer as a p-type dopant, the p-type field relaxation layer contains Al in a crystal composition, and a temperature-rise process from a growth temperature of the cap layer to a growth temperature of the light absorbing layer is performed in an inactive gas atmosphere without introducing a group V raw material.Type: ApplicationFiled: August 19, 2015Publication date: June 2, 2016Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Harunaka YAMAGUCHI, Susumu HATAKENAKA
-
Publication number: 20130109134Abstract: A method of manufacturing a semiconductor device, includes introducing a substrate into a growth furnace, forming impurity absorption layers on the substrate and on inner walls of the growth furnace, the impurity absorption layers absorbing impurities on a surface of the substrate and impurities in the growth furnace, etching and removing the impurity absorption layers and a portion of the substrate to produce a thinned substrate, forming a buffer layer on the thinned substrate, and forming semiconductor layers on the buffer layer.Type: ApplicationFiled: June 28, 2012Publication date: May 2, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Susumu HATAKENAKA, Zempei KAWAZU, Hiroyuki KAWAHARA, Takashi NAGIRA