Susumu Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: As a result of an effort made by us for the purpose of developing a therapeutic agent having a bone formation-stimulating effect by promoting the functions of osteoblasts, the present inventors discovered that a certain nitrogen-containing heterocyclic compound exhibits a potent bone formation-stimulating effect on the osteoblast and thus can serve as an excellent prophylactic or therapeutic agent against a metabolic bone disease, whereby establishing the present invention. Thus, the present invention provides a 3,6-disubstituted 1,2,4-triazolo[4,3-b]pyridazine compound or a pharmaceutically acceptable salt thereof as well as a pharmaceutical composition comprising such a compound and a pharmaceutically acceptable carrier, especially a bone-forming agent.
Abstract: This invention implements a variable-length code pipeline decoding process as hardware by providing additional bit processing means, reducing the load on external control, and clarifying encoded data shift means. For this purpose, in order to determine a code length and additional bit length, two different decode processes are executed, the overall process is separated into three stages, i.e., a stage for shifting out a code word of encoded data, a decode processing stage, and a symbol determination & additional bit processing stage, and these stages are executed in a pipeline manner.
Abstract: An apparatus has a one-dimensional DCT transformer (101) for applying the one-dimensional orthogonal transforms to n inputs and outputting n coefficients, a transposition converter (102) for transposing n×n coefficients output from the one-dimensional DCT transformer (101) and outputting every n outputs, a multiplexer (103a) for selecting one output (1004a) of the n outputs from the transposition converter (102) or one output (1003a) of the n outputs from the one-dimensional DCT transformer (101), and a selector (100) for selecting data as a combination of one output (1010a) selected by the multiplexer (103a) and remaining (n−1) outputs, which are not input to the multiplexer (103a), of the n outputs from the transposition converter (102), or the input image data, and supplying the selected data as n data to the one-dimensional DCT transformer (101).
Abstract: A decoding apparatus has: M tables for storing, in correspondence with M types of variable-length code tables, minimum code words or maximum code words of classes of variable-length code words constructing a variable-length code table; a table selector which selects one table from the M tables; N comparators which compare input coded data with the minimum code words or maximum code words outputted from the table selected by the table selector; a switch circuit and a priority encoder which obtain a class number corresponding to an initial code word of the input coded data based on results of comparison by the N comparators; a code length converter which converts the class number into a code length; and an address generator which generates an address to access a memory holding decoded data from the class number and the code length outputted said code length converter. The data outputted from the memory based on the address becomes decoded data of the input coded data.
Abstract: This invention implements a variable-length code pipeline decoding process as hardware by providing additional bit processing means, reducing the load on external control, and clarifying encoded data shift means.
Abstract: In image data coding and decoding processing, in order to improve efficiency by processing a plurality of factors in one cycle as long as possible, the factors are rearranged, in coding or decoding processing, in a predetermined scan sequence such that significant factors and 0s are paired. In addition, an appropriate scan sequence is selected in accordance with the distribution state of frequencies to further improve the efficiency.
Abstract: Whether a header information processor quickly enters a program inactive state at the timing when it issues an operation start command of an encoding process for a predetermined processing unit to a variable-length code encoder, or the header information processor enters the program inactive state upon completion of execution steps to be processed is adaptively selected in accordance with the number of execution steps. One memory is shared by the header information processor and variable-length code encoder, and address input permission means for controlling to grant permission of an address input to the memory to one of the header information processor and the variable-length code encoder is provided. The memory is used as a work area of the header information processor, and as a storage area of a variable-length code table which is looked up by the variable-length code encoder.
Abstract: A smart card comprises an IC module and an antenna for non-contact transmission. The IC module has both a contact-type function and a non-contact-type function. In the contact-type function, power reception and signal transmission/reception is effected via an electrical contact. In the non-contact-type function, power reception and signal transmission/reception is effected in a non-contact state by an electromagnetic coupling system without providing the IC card with an electrical contact. The IC module and the antenna comprise first and second coupler coils, respectively, which are disposed to be closely coupled to each other, and the IC module and the antenna are coupled in a non-contact state by transformer coupling. An antenna coil is disposed so as not to overlap an engagement portion for the IC module, which is a region of an external terminal electrode serving as a contact-type electrode, an embossing region, or a magnetic stripe region.
Abstract: Address information generated and output by an address converter for each pixel of input image data in accordance with the phase based on the position of the pixel to be coded is stored in an address storage divided into address groups which are periodically referred to. Information indicative of the occurrence probability of the pixel to be coded and phase information of the pixel are selectively output from the address storage, and an arithmetic coding is performed for the output. During the processing, update data is written in to one group while a read-out is being performed for the other group. A template is constituted by excluding a pixel which predeses one pixel, and a prediction state in each phase is divided into two parts. The template output is applied to both of the divided storage devices, and read actions are independently performed.
December 15, 1995
Date of Patent:
December 8, 1998
Canon Kabushiki Kaisha
Keiji Ishizuka, Tsutomu Ando, Koji Aoki, Susumu Igarashi
Abstract: A vehicle including a vehicle frame and a power unit suspended from the vehicle frame in a manner to reduce the amplitude of vibration generated by the power unit and also the vibration transmitted to the vehicle frame. The power unit comprises a case, an engine integrally coupled to the case, a drive wheel rotatably supported on the case, and a transmission mechanism disposed in the case for transmitted power from the engine to the drive wheel. The power unit is supported on the vehicle frame by a linkage mechanism and a cushioning unit, the engine having a center where vibratory forces are produced and an associated direction in which primary vibratory forces are produced. The linkage mechanism includes a link extending in a direction substantially normal to the engine-associated direction.