Patents by Inventor Susumu Imaoka

Susumu Imaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device internally generating internal data read timing
    Patent number: 6804153
    Abstract: A dummy circuit including a plurality of dummy cells is provided in correspondence to a predetermined number of word lines. When either one of corresponding word lines are selected, a dummy bit line equal in load to a normal bit line is driven using the plurality of dummy cells included in this dummy circuit. A potential of this dummy bit line is detected by a dummy sense amplifier, and a sense enable signal is generated. Therefore, it is possible to accurately detect a sense timing irrespectively of array architecture.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: October 12, 2004
    Assignees: Renesas Technology Corp., Renesas Device Design Corp.
    Inventors: Tomoaki Yoshizawa, Koji Nii, Susumu Imaoka
  • Semiconductor memory device internally generating internal data read timing
    Publication number: 20040042275
    Abstract: A dummy circuit including a plurality of dummy cells is provided in correspondence to a predetermined number of word lines. When either one of corresponding word lines are selected, a dummy bit line equal in load to a normal bit line is driven using the plurality of dummy cells included in this dummy circuit. A potential of this dummy bit line is detected by a dummy sense amplifier, and a sense enable signal is generated. Therefore, it is possible to accurately detect a sense timing irrespectively of array architecture.
    Type: Application
    Filed: May 28, 2003
    Publication date: March 4, 2004
    Applicants: RENESAS TECHNOLOGY CORP., RENESAS DEVICE DESIGN CORP.
    Inventors: Tomoaki Yoshizawa, Koji Nii, Susumu Imaoka