Patents by Inventor Susumu Ishida

Susumu Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7790554
    Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: September 7, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hideki Yasuoka, Masami Kouketsu, Susumu Ishida, Kazunari Saitou
  • Publication number: 20100034811
    Abstract: The present inventors focused on the fact that inflammation at the subretinal macular area enhances choroidal neovascularization, and developed pharmaceutical agents that suppress initiation or advancement of neovascularization by angiogenic factors such as VEGF. More specifically, the present inventors revealed that administering anti-IL-6 receptor monoclonal antibodies to mice treated with laser photocoagulation inhibits the development of choroidal neovascularization.
    Type: Application
    Filed: January 26, 2007
    Publication date: February 11, 2010
    Applicants: CHUGAI SEIYAKU KABUSHIKI KAISHA, KEIO UNIVERSITY
    Inventor: Susumu Ishida
  • Publication number: 20090209078
    Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se
    Type: Application
    Filed: April 29, 2009
    Publication date: August 20, 2009
    Inventors: Hideki YASUOKA, Masami Kouketsu, Susumu Ishida, Kazunari Saitou
  • Patent number: 7541661
    Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: June 2, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hideki Yasuoka, Masami Kouketsu, Susumu Ishida, Kazunari Saitou
  • Patent number: 7224037
    Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: May 29, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hideki Yasuoka, Masami Kouketsu, Susumu Ishida, Kazunari Saitou
  • Publication number: 20070096247
    Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se
    Type: Application
    Filed: December 21, 2006
    Publication date: May 3, 2007
    Inventors: Hideki Yasuoka, Masami Kouketsu, Susumu Ishida, Kazunari Saitou
  • Publication number: 20060267903
    Abstract: The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
    Type: Application
    Filed: May 26, 2006
    Publication date: November 30, 2006
    Inventors: Yasushi Kawase, Susumu Ishida, Takesada Akiba, Yasushi Nagata, Naoki Miyamoto, Kazuyoshi Shiba
  • Patent number: 6907053
    Abstract: A semiconductor laser element and a protective wall surrounding the element are provided on the surface of a metal frame of a semiconductor laser device. Circumferential portions are provided on an outer periphery of the metal frame for rotating the optical axis of light originating from a light-emitting point of the semiconductor laser element to a direction along the surface of the metal frame. By way of a guide of an optical pickup base corresponding to the circumferential portions, the semiconductor laser device is mounted on the optical pickup base.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: June 14, 2005
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsumi Electric Co., Ltd.
    Inventors: Kenji Ohgiyama, Kiyoaki Tsumura, Koji Yamashita, Toshio Takeuchi, Susumu Ishida, Kenji Kan
  • Publication number: 20040251505
    Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se
    Type: Application
    Filed: July 20, 2004
    Publication date: December 16, 2004
    Applicants: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Hideki Yasuoka, Masami Kouketsu, Susumu Ishida, Kazunari Saitou
  • Patent number: 6780717
    Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: August 24, 2004
    Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Hideki Yasuoka, Masami Kouketsu, Susumu Ishida, Kazunari Saitou
  • Publication number: 20030123499
    Abstract: A semiconductor laser element and a protective wall surrounding the element are provided on the surface of a metal frame of a semiconductor laser device. Circumferential portions are provided on an outer periphery of the metal frame for rotating the optical axis of light originating from a light-emitting point of the semiconductor laser element to a direction along the surface of the metal frame. By way of a guide of an optical pickup base corresponding to the circumferential portions, the semiconductor laser device is mounted on the optical pickup base.
    Type: Application
    Filed: June 28, 2002
    Publication date: July 3, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenji Ohgiyama, Kiyoaki Tsumura, Koji Yamashita, Toshio Takeuchi, Susumu Ishida, Kenji Kan
  • Publication number: 20030104671
    Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se
    Type: Application
    Filed: December 26, 2002
    Publication date: June 5, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Hideki Yasuoka, Masami Kouketsu, Susumu Ishida, Kazunari Saitou
  • Publication number: 20020064917
    Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se
    Type: Application
    Filed: November 21, 2001
    Publication date: May 30, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Hideki Yasuoka, Masami Kouketsu, Susumu Ishida, Kazunari Saitou
  • Patent number: D476315
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: June 24, 2003
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Toshihiko Honma, Susumu Ishida, Osamu Masakado, Kazutomo Imi