Patents by Inventor Susumu Iwamoto

Susumu Iwamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6756636
    Abstract: A lateral semiconductor device includes an alternating conductivity type layer for providing a first semiconductor current path in the ON-state of the device and for being depleted in the OFF-state of the device, that has an improved structure for realizing a high breakdown voltage in the curved sections of the alternating conductivity type layer.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: June 29, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
  • Patent number: 6724042
    Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: April 20, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
  • Publication number: 20040065921
    Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.
    Type: Application
    Filed: October 3, 2003
    Publication date: April 8, 2004
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato, Tatsuji Nagaoka
  • Patent number: 6700141
    Abstract: A reliable super-junction semiconductor device is provided that facilitates relaxing the tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an inductive load. The super-junction semiconductor device includes an active region including a thin first alternating conductivity type layer and a heavily doped n+-type intermediate drain layer between first alternating conductivity type layer and an n++-type drain layer, and a breakdown withstanding region including a thick second alternating conductivity type layer. Alternatively, active region includes a first alternating conductivity type layer and a third alternating conductivity type layer between first alternating conductivity type layer and n++-type drain layer, third alternating conductivity type layer being doped more heavily than first alternating conductivity type layer.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: March 2, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato
  • Patent number: 6696728
    Abstract: To provide a super-junction MOSFET reducing the tradeoff relation between the on-resistance and the breakdown voltage greatly and having a peripheral structure, which facilitates reducing the leakage current in the OFF-state thereof and stabilizing the breakdown voltage thereof. The vertical MOSFET according to the invention includes a drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (peripheral region) including a second alternating conductivity type layer around drain drift region, second alternating conductivity type layer being formed of layer-shaped vertically-extending n-type regions and layer-shaped vertically-extending p-type regions laminated alternately; an n-type region around second alternating conductivity type layer; and a p-type region formed in the surface portion of n-type region to reduce the leakage current in the OFF-state of the MOSFET.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: February 24, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
  • Patent number: 6693323
    Abstract: A method of manufacture reduces costs and provides an excellent mass-productivity, a super-junction semiconductor device, that facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double diffusion MOSFET manufacturing process. An oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, oxide film is removed by ion etching, and trenches are dug.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: February 17, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takahiro Sato, Katsunori Ueno, Tatsuhiko Fujihira, Kenji Kunihara, Yasuhiko Onishi, Susumu Iwamoto
  • Patent number: 6677643
    Abstract: A super-junction semiconductor is provided that facilitates easy mass-production thereof, reducing the tradeoff relation between the on-resistance and the breakdown voltage, obtaining a high breakdown voltage and reducing the on-resistance to increase the current capacity thereof. The super-junction semiconductor device includes a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer on low resistance layer, and a second alternating conductivity type layer on the first alternating conductivity type layer. The first alternating conductivity type layer including regions of a first conductivity type and regions of a second conductivity type arranged alternately with each other.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: January 13, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato
  • Patent number: 6674126
    Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: January 6, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato, Tatsuji Nagaoka
  • Publication number: 20030176031
    Abstract: A semiconductor device includes a drift region, which includes a first alternating conductivity type layer, and a peripheral region, which includes a second alternating conductivity type layer and a third alternating conductivity type layer in the surface portion of the peripheral region. The first layer includes first n-type regions and first p-type regions arranged alternately at a first pitch. The second layer is continuous with the first layer and includes second n-type regions and second p-type regions arranged alternately at the first pitch. The impurity concentration in the second layer is almost the same as the impurity concentration in the first layer. The third layer includes third n-type regions and third p-type regions arranged alternately at a second pitch. The third layer can be doped more lightly than the first and second alternating conductivity type layers. The second pitch can be the same as the first pitch or smaller.
    Type: Application
    Filed: January 30, 2003
    Publication date: September 18, 2003
    Inventors: Yasuhiko Onishi, Tatsuji Nagaoka, Susumu Iwamoto, Takahiro Sato
  • Patent number: 6621132
    Abstract: The super-junction semiconductor device, which facilitates increased switching speed and reduced on-resistance, includes an alternating conductivity type layer formed of n-type drift regions and p-type partition regions arranged alternately, a pair of the n-type drift region and p-type partition region repeating at a first repeating pitch, and trenches each containing a gate electrode buried therein, the trenches being arranged repeatedly at a second repeating pitch wider than the first repeating pitch. The device further includes one or more n-type channel regions between a p-type partition regions and a p-type well region.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: September 16, 2003
    Assignee: Fuji Electric Co., Ltds.
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato
  • Patent number: 6611021
    Abstract: A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a high breakdown voltage and to provide a method of manufacturing the semiconductor device. The vertical MOSFET according to the invention includes an alternating-conductivity-type drain drift layer on an n+-type drain layer as a substrate. The alternating-conductivity-type drain drift layer is formed of n-type drift current path regions and p-type partition regions alternately arranged laterally with each other. The n-type drift current path regions and p-type partition regions extend in perpendicular to n+-type drain layer. Each p-type partition region is formed by vertically connecting p-type buried diffusion unit regions Up. The n-type drift current path regions are residual regions, left after connecting p-type buried diffusion unit regions Up, with the conductivity type thereof unchanged.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: August 26, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
  • Publication number: 20030148559
    Abstract: A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a high breakdown voltage and to provide a method of manufacturing the semiconductor device. The vertical MOSFET according to the invention includes an alternating-conductivity-type drain drift layer on an n+-type drain layer as a substrate. The alternating-conductivity-type drain drift layer is formed of n-type drift current path regions and p-type partition regions alternately arranged laterally with each other. The n-type drift current path regions and p-type partition regions extend in perpendicular to n+-type drain layer. Each p-type partition region is formed by vertically connecting p-type buried diffusion unit regions Up. The n-type drift current path regions are residual regions, left after connecting p-type buried diffusion unit regions Up, with the conductivity type thereof unchanged.
    Type: Application
    Filed: February 28, 2003
    Publication date: August 7, 2003
    Applicant: Fuji Electric, Co., Ltd.
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
  • Patent number: 6586801
    Abstract: A semiconductor device facilitates preventing hot carriers from being injected into the insulation film so that the characteristics and the reliability of the active region thereof may not be impaired. The device includes an alternating-conductivity-type drain including heavily doped p-type breakdown voltage limiter regions in the portions of p-type partition regions in contact with the well bottoms of p-type base regions. Since the electric field in the central portion of breakdown voltage limiter regions reaches the critical value in advance to the electric field at the points E beneath gate insulation films the electric field at the points E is relaxed and hot carrier injection into gate insulation films is prevented.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: July 1, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
  • Patent number: 6576935
    Abstract: A bidirectional semiconductor device facilitates making a current flow from the first MOSFET to the second MOSFET and vice versa across low on-resistance and exhibits a high breakdown voltage. The bidirectional semiconductor device includes a first n-channel MOSFET including base regions, a second n-channel MOSFET including base regions, and an alternating conductivity type layer formed of drift region and partition regions arranged alternately. Partition regions are isolated from base regions by a high resistivity region and from base regions by a high resistivity region to maintaining a high breakdown voltage between first MOSFET and the second MOSFET. By connecting high resistivity regions and via drift regions to each other, a current is made flow from the first MOSFET to the second MOSFET and vice versa and the on-voltage is reduced.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: June 10, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
  • Publication number: 20030008483
    Abstract: A method of manufacture reduces costs and provides an excellent mass-productivity, a super-junction semiconductor device, that facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double diffusion MOSFET manufacturing process. And oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, oxide film is removed by ion etching, and trenches are dug.
    Type: Application
    Filed: September 9, 2002
    Publication date: January 9, 2003
    Applicant: Fuji Electric, Co., Ltd.
    Inventors: Takahiro Sato, Katsunori Ueno, Tatsuhiko Fujihira, Kenji Kunihara, Yasuhiko Onishi, Susumu Iwamoto
  • Publication number: 20020171093
    Abstract: To provide a super-junction MOSFET reducing the tradeoff relation between the on-resistance and the breakdown voltage greatly and having a peripheral structure, which facilitates reducing the leakage current in the OFF-state thereof and stabilizing the breakdown voltage thereof. The vertical MOSFET according to the invention includes a drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (peripheral region) including a second alternating conductivity type layer around drain drift region, second alternating conductivity type layer being formed of layer-shaped vertically-extending n-type regions and layer-shaped vertically-extending p-type regions laminated alternately; an n-type region around second alternating conductivity type layer; and a p-type region formed in the surface portion of n-type region to reduce the leakage current in the OFF-state of the MOSFET.
    Type: Application
    Filed: March 15, 2002
    Publication date: November 21, 2002
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
  • Publication number: 20020167020
    Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.
    Type: Application
    Filed: February 11, 2002
    Publication date: November 14, 2002
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato, Tatsuji Nagaoka
  • Patent number: 6475864
    Abstract: A method of manufacturing reduces costs and provides an excellent mass-productivity, super-junction semiconductor device, which facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double difflusion MOSFET manufacturing process. An oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, the oxide film is removed by ion etching, and trenches are dug.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: November 5, 2002
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takahiro Sato, Katsunori Ueno, Tatsuhiko Fujihira, Kenji Kunihara, Yasuhiko Onishi, Susumu Iwamoto
  • Publication number: 20020088990
    Abstract: A reliable super-junction semiconductor device is provided that facilitates relaxing the tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an inductive load. The super-junction semiconductor device includes an active region including a thin first alternating conductivity type layer and a heavily doped n+-type intermediate drain layer between first alternating conductivity type layer and an n++-type drain layer, and a breakdown withstanding region including a thick second alternating conductivity type layer. Alternatively, active region includes a first alternating conductivity type layer and a third alternating conductivity type layer between first alternating conductivity type layer and n++-type drain layer, third alternating conductivity type layer being doped more heavily than first alternating conductivity type layer.
    Type: Application
    Filed: October 17, 2001
    Publication date: July 11, 2002
    Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato
  • Publication number: 20020060330
    Abstract: A bidirectional semiconductor device facilitates making a current flow from the first MOSFET to the second MOSFET and vice versa across low on-resistance and exhibits a high breakdown voltage. The bidirectional semiconductor device includes a first n-channel MOSFET including base regions, a second n-channel MOSFET including base regions, and an alternating conductivity type layer formed of drift region and partition regions arranged alternately. Partition regions are isolated from base regions by a high resistivity region and from base regions by a high resistivity region to maintaining a high breakdown voltage between first MOSFET and the second MOSFET. By connecting high resistivity regions and via drift regions to each other, a current is made flow from the first MOSFET to the second MOSFET and vice versa and the on-voltage is reduced.
    Type: Application
    Filed: June 28, 2001
    Publication date: May 23, 2002
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato