Patents by Inventor Susumu Kagohashi

Susumu Kagohashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240196526
    Abstract: A wiring substrate includes insulating layers including inorganic particles and resin, conductor layers formed on first surfaces of the insulating layers, respectively, and including the outermost conductor layer and a conductor layer, and via conductors formed in the insulating layers such that the via conductors are connecting the conductor layers formed on the first surfaces of the insulating layers. The conductor layers are formed such that the outermost conductor layer includes first conductor pads positioned to mount a first component and second conductor pads positioned to mount a second component and that the conductor layer includes first wiring patterns connecting the first conductor pads and the second conductor pads, and the insulating layers are formed such that the first surfaces of the insulating layers are formed of the resin and do not have exposed surfaces of the inorganic particles.
    Type: Application
    Filed: November 29, 2023
    Publication date: June 13, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Toshiki FURUTANI, Masashi KUWABARA, Susumu KAGOHASHI
  • Publication number: 20240179853
    Abstract: A wiring substrate includes an insulating layer including inorganic particles and resin, a seed layer formed on a surface of the insulating layer, and a conductor layer including a conductor pattern and formed on the seed layer. The surface of the insulating layer is a roughened surface formed such that the roughened surface of the insulating layer has exposed portions of the inorganic particles and resin with gaps at interfaces where the inorganic particles and the resin are in contact, and the seed layer is formed on the roughened surface of the insulating layer such that the seed layer is formed along the exposed portions of the inorganic particles and resin exposed on the roughened surface of the insulating layer and is not formed in the gaps at the interfaces where the inorganic particles and the resin are in contact.
    Type: Application
    Filed: November 27, 2023
    Publication date: May 30, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Susumu KAGOHASHI, Jun SAKAI
  • Publication number: 20240107684
    Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer having an opening, a second conductor layer including a seed layer and an electrolytic plating layer formed on the seed layer, and a via conductor including the seed and electrolytic plating layers and connecting the first and second conductor layers. The seed layer has a first portion on the surface of the insulating layer, a second portion on an inner wall surface in the opening of the insulating layer, and a third portion on a portion of the first conductor layer exposed by the opening of the insulating layer such that the first portion is thicker than the second and third portions, and the insulating layer includes resin and inorganic particles including first particles forming the inner wall surface and second particles embedded in the insulating layer and having shapes different from shapes of the first particles.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 28, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Jun SAKAI, Takuya INISHI, Susumu KAGOHASHI
  • Publication number: 20240107685
    Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer having an opening, a second conductor layer including a seed layer and an electrolytic plating layer formed on the seed layer, and a via conductor including the seed layer and the electrolytic plating layer and connecting the first conductor and second conductor layers. The seed layer has a first portion on the surface of the insulating layer, a second portion on an inner wall surface in the opening of the insulating layer, and a third portion on a portion of the first conductor layer exposed by the opening of the insulating layer such that the first portion is thicker than the second portion and the third portion, the second portion has a first film and a second film electrically connected to the first film, and a portion of the first film is formed on the second film.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 28, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Susumu KAGOHASHI, Jun SAKAI, Kyohei YOSHIKAWA, Takuya INISHI
  • Publication number: 20240098892
    Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer laminated on the first conductor layer and including resin material and inorganic particles, a second conductor layer formed on a first surface of the insulating layer such that the first conductor layer is facing a second surface of the insulating layer, and a via conductor formed in an opening extending through the insulating layer and connecting the first and second conductor layers. The insulating layer is formed such that the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin, the first inorganic particles have first portions protruding from the resin and second portions embedded in the resin respectively, and the first surface of the resin insulating layer includes a surface of the resin and surfaces of the first portions exposed from the surface of the resin.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 21, 2024
    Applicant: IBIDEN CO., LTD.
    Inventors: Susumu KAGOHASHI, Jun SAKAI, Kyohei YOSHIKAWA
  • Publication number: 20230328882
    Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the resin insulating layer, and a via conductor formed in an opening formed in the resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer. The via conductor is formed such that the via conductor includes a seed layer covering an inner wall surface of the resin insulating layer inside of the opening and an electrolytic plating layer formed on the seed layer such that the seed layer has a plurality of columnar parts grown in columnar shapes.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 12, 2023
    Applicant: IBIDEN CO., LTD.
    Inventor: Susumu KAGOHASHI
  • Publication number: 20230319986
    Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the insulating layer, and a via conductor formed in an opening formed in the insulating layer such that the via conductor is connecting the first and second conductor layers. The second conductor layer and via conductor include a seed layer and an electrolytic plating layer formed on the seed layer such that the seed layer has a first portion formed on the surface of the insulating layer, a second portion formed on an inner wall surface of the insulating layer in the opening, and a third portion formed on the first conductor layer exposed from the opening and that the first portion has a thickness that is greater than a thickness of the second portion and a thickness of the third portion.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 5, 2023
    Applicant: IBIDEN CO., LTD.
    Inventor: Susumu KAGOHASHI
  • Publication number: 20230080335
    Abstract: A printed wiring board includes a resin insulating layer including resin and particles, and a conductor layer formed on a surface of the resin insulating layer. The particles in the resin insulating layer include first particles and second particles such that the first particles are partially embedded in the resin and the second particles are completely embedded in the resin, and the resin insulating layer is formed such that the first particles has exposed surfaces exposed from the resin and covered surfaces covered by the resin, respectively, the surface of the resin insulating layer includes the first exposed surfaces, and a ratio of a second area to a first area is in a range of 0.1 to 0.25 where the first area is an area of the surface of the resin insulating layer, and the second area is obtained by summing areas of the exposed surfaces of the first particles.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 16, 2023
    Applicant: IBIDEN CO., LTD.
    Inventors: Satoru KAWAI, Katsuhiko TANNO, Susumu KAGOHASHI, Kentaro WADA
  • Publication number: 20230071257
    Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the resin insulating layer and including a signal wiring, and a via conductor formed in the resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer. The resin insulating layer has an opening such that the opening is exposing a portion of the first conductor layer and that the via conductor is formed in the opening of the resin insulating layer, and the resin insulating layer includes inorganic particles and resin such that the resin is forming the surface of the resin insulating layer.
    Type: Application
    Filed: August 29, 2022
    Publication date: March 9, 2023
    Applicant: IBIDEN CO., LTD.
    Inventors: Susumu KAGOHASHI, Maaya TOMIDA
  • Patent number: 6645297
    Abstract: A roll coater with which an interlaminar resin insulating layer and/or a solder resist layer can be formed with good thickness uniformity to enable the manufacture of a printed circuit board free from the no-hole defect and anomalies in the diameter and geometry of the holes for via-hole and/or solder bump which is due to uneven layer thickness, thus having high electrical integrity and reliability.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: November 11, 2003
    Assignees: Ibiden Co., Ltd., Kabushiki Kaisha Toyoda Jidoshokki Seisakusho
    Inventors: Ayumi Suzuki, Ayao Niki, Ryo Aoki, Kazuhisa Kitajima, Susumu Kagohashi, Yukari Kajiyama, Hiroshi Tanaka