Patents by Inventor Susumu Kajita

Susumu Kajita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9947921
    Abstract: A silicon-carbon composite material includes: layers of carbon material; and secondary particles of silicon held between the layers of the carbon material. Each of the secondary particles of silicon is an aggregate of primary particles of silicon. At least one of the primary particles of silicon has a diameter 3 nm or more. At least one of the secondary particles of silicon has a diameter of 50 nm or less.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: April 17, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Susumu Kajita
  • Publication number: 20170352878
    Abstract: A silicon—carbon composite material contains: a carbon material comprising layers; and silicon particles supported between the layers of the carbon material. The specific surface area of the silicon—carbon composite material is 200 m2/g or more as determined by the BET method using nitrogen gas adsorption.
    Type: Application
    Filed: May 16, 2017
    Publication date: December 7, 2017
    Inventor: SUSUMU KAJITA
  • Publication number: 20160380265
    Abstract: A silicon-carbon composite material includes: layers of carbon material; and secondary particles of silicon held between the layers of the carbon material. Each of the secondary particles of silicon is an aggregate of primary particles of silicon. At least one of the primary particles of silicon has a diameter 3 nm or more. At least one of the secondary particles of silicon has a diameter of 50 nm or less.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 29, 2016
    Inventor: SUSUMU KAJITA
  • Patent number: 8745426
    Abstract: An information processing apparatus has a task area unit as an area that executes a predetermined process, a power control unit that reads a task area to execute the process from the process and supplies power from a power source to the read task area, and a control unit that executes the process in the task area unit to which the power is supplied by the power control unit.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: June 3, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Machida, Satoshi Oguni, Susumu Kajita, Yuko Ishibashi, Hitoshi Ueno
  • Publication number: 20120023349
    Abstract: An information processing apparatus has a task area unit as an area that executes a predetermined process, a power control unit that reads a task area to execute the process from the process and supplies power from a power source to the read task area, and a control unit that executes the process in the task area unit to which the power is supplied by the power control unit.
    Type: Application
    Filed: July 20, 2011
    Publication date: January 26, 2012
    Inventors: Shinichi MACHIDA, Satoshi OGUNI, Susumu KAJITA, Yuko ISHIBASHI, Hitoshi UENO
  • Publication number: 20020127852
    Abstract: Disclosed is a technique capable of suppressing the damage of a semiconductor manufacturing apparatus due to the breakage or the crack to the minimum by surely detecting the breakage or the crack on a part of a wafer in a semiconductor manufacturing apparatus of a multi-chamber system. An entire image of a wafer is photographed by a camera in each time when the wafer is processed, and the photographed image is processed by a discrimination unit, thereby determining the presence of the breakage or the crack on the wafer. When the breakage or the crack is detected, an error signal is transmitted from the discrimination unit to a computer that controls the semiconductor manufacturing apparatus, and the operations of the process chamber and the transport chamber used immediately before the detection of the breakage or the crack on the wafer are stopped.
    Type: Application
    Filed: March 1, 2002
    Publication date: September 12, 2002
    Inventors: Kazuya Kawakami, Yukihiro Suzuki, Ken Okutani, Susumu Kajita, Takeshi Hashimoto
  • Patent number: 5744411
    Abstract: An aluminum nitride sintered product with a high thermal conductivity (at least 100 W/m.K) can be prepared at a sintering temperature of less than 1850.degree. C. (often less than 1650.degree. C.) using a sinterable combination of aluminum nitride powder with at least three sintering aids. The sintering aids include a source of a rare earth metal oxide, a source of an alkaline earth metal oxide, a boron source and, optionally, a source of aluminum oxide. The sinterable combinations may also be used to prepare cofired, multilayer substrates.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: April 28, 1998
    Assignee: The Dow Chemical Company
    Inventors: JunHong Zhao, Theresa A. Guiton, Yi-Hung Chiao, William Rafaniello, Noboru Hashimoto, Kyoji Tanaka, Susumu Kajita, Hiroyoshi Yoden
  • Patent number: 5330692
    Abstract: An aluminum nitride (AlN) sintered product with a high thermal conductivity of 120 W/m.multidot.k or above can be produced at a relatively low sintering temperature of 1650.degree. C. or below in accordance with the following process of the present invention. That is, an A1N powder having a specific surface in a region of about 3.5 to 8 m.sup.2 /g and an oxygen content between 0.5 to 1.8 wt % is mixed with optimum additive amounts of sintering aids (I) to (III) to obtain a mixture powder. The sintering aid (I) is at least one selected from the group consisting of rare earth oxides and rare earth compounds which are converted to corresponding rare earth oxides by the sintering. The sintering aid (II) is at least one selected from the group consisting of alkaline earth oxides and alkaline earth compounds which are converted to corresponding alkaline earth oxides by the sintering. The sintering aid (III) is at least one selected from the group consisting of LAB.sub.6, NbC, and WB.
    Type: Grant
    Filed: July 12, 1993
    Date of Patent: July 19, 1994
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Noboru Hashimoto, Kyoji Tanaka, Susumu Kajita, Hiroyoshi Yoden
  • Patent number: 4865877
    Abstract: A method for roughening a ceramic substrate surface includes a step of sequentially taking out part of roughening a treatment bath of phosphoric acid into which the ceramic substrate is dipped prior to a formation on the substrate of conductor a layer, and subjecting the part of the bath taken out sequentially to regeneration treatment. Any increase in the viscosity due to dehydrating condensation of the roughening bath can be thereby effectively restrained to prolong effective life of the bath. Further, the surface roughened ceramic substrate can be provided thereon with conductor layers smoothly formed by means of a plating and eventually with a circuit pattern as well as a resistor formed on the pattern within an inert gas atmosphere.
    Type: Grant
    Filed: October 27, 1987
    Date of Patent: September 12, 1989
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Noboru Yamaguchi, Satoru Ogawa, Susumu Kajita, Izuru Yoshizawa, Kiyotaka Waki, Masayuki Ishihara