Patents by Inventor Susumu Maniwa
Susumu Maniwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12101074Abstract: A multilayer circuit board with an LC resonant circuit that has an electronic component package including the multilayer circuit board with the LC resonant circuit are provided. The multilayer circuit board with the LC resonant circuit configured by alternately laminating conductive layers and insulating resin layers on both sides of a core substrate includes a first set of wiring lines, a set of vias, and a second set of wiring lines. The first set of wiring lines configures both ends of the LC resonant circuit and is formed in a first one of the conductive layers. The set of vias extends through the insulating resin layers. The second set of wiring lines is connected to an input/output terminal of the LC resonant circuit and is formed in a second one of the conductive layers. The first set of wiring lines is connected to the second set of wiring lines.Type: GrantFiled: December 15, 2021Date of Patent: September 24, 2024Assignee: TOPPAN INC.Inventors: Noriko Kanou, Susumu Maniwa
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Patent number: 11877394Abstract: A glass core multilayer wiring board includes a glass substrate, a through electrode, a first layer structure, and a second layer structure. A through hole has a diameter decreasing from a first surface toward a second surface. The through electrode is along a side wall of the through hole. The first layer structure is on the first surface and the second layer structure is on the second surface. The second layer structure closes an opening in the second surface defining a bottom section. The through electrode has: a first layer on part of the side wall and on part or all of the bottom section of the through hole closing the opening of the through hole, a second layer covering the first layer, the side wall of the through hole exposed, and the bottom section, and a third layer is located on the second layer.Type: GrantFiled: May 17, 2022Date of Patent: January 16, 2024Assignee: TOPPAN INC.Inventors: Susumu Maniwa, Masashi Sawadaishi
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Publication number: 20230111374Abstract: A multilayer wiring substrate and a module having the multilayer wiring substrate, wherein the multilayer wiring substrate has a capacitor with a capacitance value smaller than that of the conventional one. The substrate includes a core substrate and capacitors installed therein. At least one of the capacitors is a first capacitor which includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is located closer to the core substrate than the dielectric layer and the upper electrode are. The upper electrode is located farther away from the core substrate than the dielectric layer and the lower electrode are. The lower electrode is entirely disposed on the core substrate. The upper electrode has a first portion and a second portion. The first portion overlaps the dielectric layer and the lower electrode to serve as the first capacitor. The second portion extends from the first portion.Type: ApplicationFiled: November 17, 2022Publication date: April 13, 2023Applicant: TOPPAN INC.Inventors: Noriko KANO, Tomoyuki SHIRASAKI, Susumu MANIWA
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Publication number: 20230039184Abstract: A glass core wiring substrate incorporating a high-frequency filter having good high-frequency characteristics as a core material and allowing a more efficient arrangement of a conductor in the glass substrate, a module including the same, and a method of manufacturing the glass core wiring substrate incorporating a high-frequency filter. A conductive layer in a glass through a hole in a glass core substrate has a structure in which a hollow cylindrical conductor layer on a side wall of the glass through hole is connected to a cover conductor layer covering one of two openings of the glass through hole. To achieve such a structure, a carrier is attached to one surface of the glass core substrate to cover one of the openings of the glass through hole, and the carrier is peeled off and removed after lamination of the conductor.Type: ApplicationFiled: October 5, 2022Publication date: February 9, 2023Applicant: TOPPAN INC.Inventor: Susumu MANIWA
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Publication number: 20220279651Abstract: A glass core multilayer wiring board includes a glass substrate, a through electrode, a first layer structure, and a second layer structure. A through hole has a diameter decreasing from a first surface toward a second surface. The through electrode is along a side wall of the through hole. The first layer structure is on the first surface and the second layer structure is on the second surface. The second layer structure closes an opening in the second surface defining a bottom section. The through electrode has: a first layer on part of the side wall and on part or all of the bottom section of the through hole closing the opening of the through hole, a second layer covering the first layer, the side wall of the through hole exposed, and the bottom section, and a third layer is located on the second layer.Type: ApplicationFiled: May 17, 2022Publication date: September 1, 2022Applicant: TOPPAN INC.Inventors: Susumu MANIWA, Masashi SAWADAISHI
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Patent number: 11303261Abstract: A circuit board has a glass core in which a through hole is formed, and a conductor pattern is formed on an inner peripheral wall of the through hole and a surface of the glass core to form a circuit element including a solenoid coil element and a capacitor element. Accordingly, a low-cost and compact circuit board capable of supporting high-capacity communication for thin mobile communication devices such as smartphones can be provided. Since the circuit board can be electrically connected to at least one of the electronic components such as a switch, an amplifier, and a filter via one terminal, and can be electrically connected to a mother board via another terminal, it has integrated functions, and can be suitably used for thin mobile communication devices such as smartphones.Type: GrantFiled: November 20, 2020Date of Patent: April 12, 2022Assignee: TOPPAN PRINTING CO., LTD.Inventors: Tomoyuki Shirasaki, Hironori Nomura, Noriko Kanou, Susumu Maniwa, Jun Onohara
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Publication number: 20220109416Abstract: A multilayer circuit board with an LC resonant circuit that has an electronic component package including the multilayer circuit board with the LC resonant circuit are provided. The multilayer circuit board with the LC resonant circuit configured by alternately laminating conductive layers and insulating resin layers on both sides of a core substrate includes a first set of wiring lines, a set of vias, and a second set of wiring lines. The first set of wiring lines configures both ends of the LC resonant circuit and is formed in a first one of the conductive layers. The set of vias extends through the insulating resin layers. The second set of wiring lines is connected to an input/output terminal of the LC resonant circuit and is formed in a second one of the conductive layers. The first set of wiring lines is connected to the second set of wiring lines.Type: ApplicationFiled: December 15, 2021Publication date: April 7, 2022Applicant: TOPPAN INC.Inventors: Noriko KANOU, Susumu MANIWA
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Publication number: 20210143787Abstract: A circuit board has a glass core in which a through hole is formed, and a conductor pattern is formed on an inner peripheral wall of the through hole and a surface of the glass core to form a circuit element including a solenoid coil element and a capacitor element. Accordingly, a low-cost and compact circuit board capable of supporting high-capacity communication for thin mobile communication devices such as smartphones can be provided. Since the circuit board can be electrically connected to at least one of the electronic components such as a switch, an amplifier, and a filter via one terminal, and can be electrically connected to a mother board via another terminal, it has integrated functions, and can be suitably used for thin mobile communication devices such as smartphones.Type: ApplicationFiled: November 20, 2020Publication date: May 13, 2021Applicant: TOPPAN PRINTING CO.,LTD.Inventors: Tomoyuki SHIRASAKI, Hironori NOMURA, Noriko KANOU, Susumu MANIWA, Jun ONOHARA
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Patent number: 8703598Abstract: A manufacturing method of a lead frame substrate includes: applying a photosensitive resist or a dry film to first and second surfaces of a metal plate; pattern-exposing the photosensitive resist or the dry film, and then developing the first surface and the second surface to form on the first surface a first resist pattern for forming a connection post and to form on the second surface a second resist pattern for forming a wiring pattern; etching the first surface partway down the metal plate to form the connection post; filling the first surface with a pre-molding resin to a thickness with which the etched surface is buried; removing the pre-molding resin uniformly in a thickness direction of the pre-molding resin until a bottom surface of the connection post is exposed; and etching the second surface to form a wiring pattern.Type: GrantFiled: September 26, 2013Date of Patent: April 22, 2014Assignee: Toppan Printing Co., Ltd.Inventors: Susumu Maniwa, Takehito Tsukamoto, Junko Toda
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Publication number: 20140021162Abstract: A manufacturing method of a lead frame substrate includes: applying a photosensitive resist or a dry film to first and second surfaces of a metal plate; pattern-exposing the photosensitive resist or the dry film, and then developing the first surface and the second surface to form on the first surface a first resist pattern for forming a connection post and to form on the second surface a second resist pattern for forming a wiring pattern; etching the first surface partway down the metal plate to form the connection post; filling the first surface with a pre-molding resin to a thickness with which the etched surface is buried; removing the pre-molding resin uniformly in a thickness direction of the pre-molding resin until a bottom surface of the connection post is exposed; and etching the second surface to form a wiring pattern.Type: ApplicationFiled: September 26, 2013Publication date: January 23, 2014Applicant: TOPPAN PRINTING CO., LTD.Inventors: Susumu Maniwa, Takehito Tsukamoto, Junko Toda
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Patent number: 8558363Abstract: A lead frame substrate, includes: a metal plate having first and second surfaces; a semiconductor element mounting section, semiconductor element electrode connection terminals, and a first outer frame section formed on the first surface; external connection terminals formed on the second surface and electrically connected with the semiconductor element electrode connection terminals; a second outer frame section formed on the second surface; and a resin layer formed on a gap between the first outer frame and the second outer frame. Each external connection terminal buried in the resin layer has at least one projection formed on a side surface thereof throughout a side lower portion of the first surface.Type: GrantFiled: March 10, 2011Date of Patent: October 15, 2013Assignee: Toppan Printing Co., Ltd.Inventors: Takehito Tsukamoto, Susumu Maniwa, Junko Toda, Yasuhiro Sakai
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Patent number: 8546940Abstract: A lead frame substrate, including: a metal plate with a first surface and a second surface; a connection post formed on the first surface; wiring formed on the second surface; and a pre-molding resin layer, in which a thickness of the pre-molding resin layer is the same as a height of the connection post.Type: GrantFiled: September 29, 2009Date of Patent: October 1, 2013Assignee: Toppan Printing Co., Ltd.Inventors: Susumu Maniwa, Takehito Tsukamoto, Junko Toda
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Patent number: 8535987Abstract: A manufacturing method of a substrate for a semiconductor element, wherein a first step includes: forming a first and second photosensitive resin layer on a first and second surface of a metal plate, respectively; forming a first and second resist pattern on the first and second surface, for forming a connection post and a wiring pattern, respectively. A second step includes: forming the connection post and wiring pattern; filling in a premold liquid resin to the first surface which was etched; forming a premold resin layer by hardening the premold liquid resin; performing a grinding operation on the first surface, and exposing an upper bottom surface of the connection post from the premold resin layer. A groove structure is formed by the first and second steps, wherein a depth of the groove is up to an intermediate part in a thickness direction of the metal plate.Type: GrantFiled: September 30, 2011Date of Patent: September 17, 2013Assignee: Toppan Printing Co., Ltd.Inventors: Susumu Maniwa, Takehito Tsukamoto, Junko Toda
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Patent number: 8535979Abstract: A manufacturing method of a semiconductor element substrate including: forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; forming a second photoresist pattern on the second surface of the metallic plate; forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; forming a plurality of concaved parts on the second surface of the metallic plate; forming a resin layer by injecting a resin to the plurality of concaved parts; and etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.Type: GrantFiled: October 31, 2012Date of Patent: September 17, 2013Assignee: Toppan Printing Co., Ltd.Inventors: Junko Toda, Susumu Maniwa, Takehito Tsukamoto
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Patent number: 8466547Abstract: Provided is a manufacturing method of a substrate for a semiconductor element including the steps of: providing a first photosensitive resin layer on a first surface of a metal plate; providing a second photosensitive resin layer on a second surface different from the first surface of the metal plate; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring pattern on the second surface of the metal plate; forming the connection post by performing an etching from the first surface to a midway of the metal plate; filling in a premold resin to a portion of the first surface where the connection post does not exist; processing so that a height of the connection post of the first surface is lower than a height of the premold resin surrounding the connection post; and forming the wiring pattern by performing an etching on the second surface.Type: GrantFiled: September 30, 2011Date of Patent: June 18, 2013Assignee: Toppan Printing Co., Ltd.Inventors: Susumu Maniwa, Takehito Tsukamoto, Junko Toda
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Patent number: 8390105Abstract: A lead frame substrate, including: a metal plate having a first surface and a second surface; a semiconductor element mount portion and a semiconductor element electrode connection terminal that are formed on the first surface; an external connection terminal formed on the second surface and electrically connected to the semiconductor element electrode connection terminal; a conducting wire that connects the semiconductor element electrode connection terminal and the external connection terminal to each other; a resin layer formed on the metal plate; a hole portion that is partly formed in the second surface of the metal plate and does not penetrate the metal plate; and a plurality of protrusions that are formed on a bottom surface of the hole portion and protrude in a direction away from the metal plate, the protrusions having a height lower than a position of the second surface, not being in electrical conduction with the conducting wire, and being dispersed separately.Type: GrantFiled: September 28, 2009Date of Patent: March 5, 2013Assignee: Toppan Printing Co., Ltd.Inventors: Junko Toda, Susumu Maniwa, Yasuhiro Sakai, Takehito Tsukamoto
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Patent number: 8319322Abstract: Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.Type: GrantFiled: September 23, 2011Date of Patent: November 27, 2012Assignee: Toppan Printing Co., Ltd.Inventors: Junko Toda, Susumu Maniwa, Takehito Tsukamoto
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Patent number: 8304294Abstract: A method includes: forming a photoresist pattern to form each of a semiconductor element mounting section on which a semiconductor element is mounted, semiconductor element electrode connection terminals for connection with electrodes of the semiconductor element, and a first outer frame section on a first surface of a metal plate; forming a photoresist pattern to form each of external connection terminals, a second outer frame section, and grooves in at least a part of the second outer frame section on a second surface of the metal plate; etching a metal plate exposing section, in which the metal plate of the second surface is exposed, to form holes that do not pass through the metal plate exposing section and grooves that run from an inside to an outside of the second outer frame section; coating a pre-mold resin on the holes and the grooves, and heating the pre-mold resin under pressure using a flat-bed press to form a resin layer; and etching the first surface to form the semiconductor element mounting seType: GrantFiled: March 17, 2011Date of Patent: November 6, 2012Assignee: Toppan Printing Co., Ltd.Inventors: Takehito Tsukamoto, Susumu Maniwa, Junko Toda
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Publication number: 20120061829Abstract: A manufacturing method of a substrate for a semiconductor element, wherein a first step includes: forming a first and second photosensitive resin layer on a first and second surface of a metal plate, respectively; forming a first and second resist pattern on the first and second surface, for forming a connection post and a wiring pattern, respectively. A second step includes: forming the connection post and wiring pattern; filling in a premold liquid resin to the first surface which was etched; forming a premold resin layer by hardening the premold liquid resin; performing a grinding operation on the first surface, and exposing an upper bottom surface of the connection post from the premold resin layer. A groove structure is formed by the first and second steps, wherein a depth of the groove is up to an intermediate part in a thickness direction of the metal plate.Type: ApplicationFiled: September 30, 2011Publication date: March 15, 2012Applicant: TOPPAN PRINTING CO., LTD.Inventors: Susumu MANIWA, Takehito Tsukamoto, Junko Toda
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Publication number: 20120061809Abstract: Provided is a manufacturing method of a substrate for a semiconductor element, the manufacturing method including the steps of: providing a first photosensitive resin layer at a first surface of a metal plate; providing a second photosensitive resin layer at a second surface of the metal plate different from the first surface; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring post on the second surface of the metal plate; forming the connection post by performing an etching on the first surface of the metal plate from a first surface side to a midway of the metal plate; applying a premold resin in liquid form to the first surface of the metal plate which underwent the etching on the first surface; forming a premold resin layer by solidifying the premold resin in liquid form being applied; and forming a wiring pattern by performing an etching on the second surface of the metal plate from a second surface side.Type: ApplicationFiled: September 16, 2011Publication date: March 15, 2012Applicant: TOPPAN PRINTING CO., LTDInventors: Junko TODA, Susumu Maniwa, Yasuhiro Sakai, Takehito Tsukamoto