Patents by Inventor Susumu Muramoto

Susumu Muramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Manufacturing process for semiconductor integrated circuits
    Patent number: 4566940
    Abstract: A semiconductor integrated circuit in which layers such as an field isolation region, a gate electrode, interlayer insulating films and interconnection lines are formed by the combined use of a lift-off process and an ECR plasma deposition process. According to the present invention, even if vertical dimensions of patterns of the respective layers are large as compared with their lateral dimensions, the upper surfaces of the respective layers can be planarized, permitting the fabrication of an LSI of high packing density, high operating speed and high reliability which is free from shorting and breakage of the interconnection lines.
    Type: Grant
    Filed: October 17, 1984
    Date of Patent: January 28, 1986
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Manabu Itsumi, Kohei Ehara, Susumu Muramoto, Seitaro Matsuo
  • Semiconductor device and manufacturing process thereof
    Patent number: 4564997
    Abstract: A semiconductor device in which a film of an insulator a conductor is closely deposited in a groove formed in a semiconductor substrate or an insulating or conductor layer thereon to planarize the surface thereof.A semiconductor device manufacturing process in which a specimen is selectively etched away through using a resist pattern as a mask, a pattern forming film is deposited by a plasma deposition technique on the specimen, and the resist film is removed, whereby the pattern forming film closed fills up a groove formed by etching to provide a planarized surface.
    Type: Grant
    Filed: April 16, 1982
    Date of Patent: January 21, 1986
    Assignee: Nippon-Telegraph and Telephone Public Corporation
    Inventors: Seitaro Matsuo, Susumu Muramoto, Kohei Ehara, Manabu Itsumi
  • Semiconductor integrated circuits and manufacturing process thereof
    Patent number: 4543592
    Abstract: A semiconductor integrated circuit in which layers such as an field isolation region, a gate electrode, interlayer insulating films and interconnection lines are formed by the combined use of a lift-off process and an ECR plasma deposition process. According to the present invention, even if vertical dimensions of patterns of the respective layers are large as compared with their lateral dimensions, the upper surfaces of the respective layers can be planarized, permitting the fabrication of an LSI of high packing density, high operating speed and high reliability which is free from shorting and breakage of the interconnection lines.
    Type: Grant
    Filed: November 9, 1984
    Date of Patent: September 24, 1985
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Manabu Itsumi, Kohei Ehara, Susumu Muramoto, Seitaro Matsuo
  • Method for the manufacture of semiconductor device using refractory metal in a lift-off step
    Patent number: 4448800
    Abstract: A semiconductor manufacturing method which uses a refractory metal as a lift-off material and employs, in combination, a dry etching process suitable for forming a miniature pattern without undercutting and a film deposition method for deposing the lift-off material with directionality in a direction perpendicular to the substrate surface. A semiconductor device is fabricated by a lift-off method which is free from the fear of contamination, permits easy lift off of the lift-off material, even if large in area, and hence suitable for the formation of a high-density pattern.
    Type: Grant
    Filed: July 30, 1982
    Date of Patent: May 15, 1984
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Kohei Ehara, Susumu Muramoto, Takashi Morimoto, Seitaro Matsuo, Manabu Itsumi