Abstract: A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

Abstract: A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and in parallel controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

Abstract: A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

Abstract: A vector point of an exception handler related to TLB miss exception events is obtained by reading a vector base address of a register VBR one time, and by adding a vector offset (H'400) thereto. A vector point of an exception handler related to exception events other than the TLB miss exception events is obtained by adding a vector offset to a value (vector base address) of the register VBR, and an exception code which is an address offset obtained by reading a value of the register EXPEVT or INTEVT one time is added to the vector point that is obtained. Thus, the processing is branched to a required exception handler to execute the exception event processing related to exception events other than the TLB miss exception events.

Abstract: A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

Abstract: A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and in parallel controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

Abstract: A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

Abstract: A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

Abstract: A microcomputer has a clock generator capable of changing the frequency of an output clock signal: and a power circuit capable of changing the level of an operating voltage to be outputted. The frequencies of clock signals and the levels of operating voltages to be individually fed to a plurality of circuit modules can be dynamically changed according to the content of a packaged register. If the content of the register instructs the reduction of the clock signal frequency and the operating voltage in its absolute value, the operating voltage is lowered in its absolute value prior to the change in the clock signal frequency. On the contrary, if the instruction is to increase the frequency of the clock signal and the operating voltage in its absolute value, the clock signal having the increased frequency is outputted prior to the increase of the operating voltage in the absolute value.

Abstract: A microprocessor incorporating a PLL circuit using a clock pulse having a relatively low frequency as an input clock signal of a reference frequency to form an oscillating pulse of a relatively high frequency by multiplying the input clock signal. In the microprocessor, the operation of the PLL circuit is stopped in the low-speed mode to supply the clock pulse of the relatively low frequency to the microprocessor as a system clock signal, and, in the high-speed mode, the PLL circuit is activated upon reception of an event requiring high-speed processing. Until the operation of the PLL circuit is stabilized and the request for high-speed processing comes, the above-mentioned clock pulse having the relatively low frequency is kept supplied continuously to the microprocessor as the system clock signal. This novel setup permits the high-speed switching of the microprocessor from the operating mode to the high-speed operating mode.

Abstract: A logic LSI has a plurality of modules such as a CPU contained in one chip. Frequency changing conditions, signals for designating modules whose frequencies are changed for each frequency changing condition, and signals for designating frequencies to be changed are stored in a storage device of a frequency controller, software-wise. The sequentially-input status of the logic LSI is compared with the stored frequency changing conditions and, when the former conforms to the latter, a signal for changing the corresponding frequency is applied to each of the plurality of modules. Each of the modules generates a plurality of internal clocks in synchronization with the basic clock and selects one out of the internal clocks according to the frequency changing signal.

Abstract: An input apparatus capable of concurrently accommodating itself to any external signal from a different hydraulic control system or the like. The apparatus includes electrical load sensors each arranged on a push rod or block for detecting the amount of operation of a control lever to generate an electrical signal corresponding to the amount of operation of the control lever. Also, an input apparatus which is capable of concurrently responding to both a signal generated by itself and an external signal fed thereto is provided. The apparatus includes a pilot section for exerting force which permits a shuttle to be moved against coiled compression springs. The pilot section is fed with a signal from an external hydraulic control system.

Abstract: An address of a branch instruction, a branch target address thereof, and a type thereof are stored as branch history information in a branch instruction buffer. In addition, a return address for a return from a subroutine is retained in a return buffer. A look-up operation is conducted through the buffer by using the pre-fetch address such that when a hit occurs, a branch target address is output from the buffer depending on a branch instruction type. Consequently, the branch processing is achieved at a high speed. Particularly, the processing speed of an unconditional branch instruction containing a return instruction is increased.

Abstract: An instruction fetch unit IU in a microprocessor capable of decoding two instructions in parallel fetches first and second instructions of the shortest instructions in one cycle. The fetched first instruction is supplied to and decoded by a first instruction decoder ID0, while the fetched second instruction is supplied to and decoded by a second instruction decoder ID1. In a case where an instruction having a bit width longer than the shortest instruction has been fetched by the instruction fetch unit IU, information to be decoded by the second instruction decoder ID1 is the non-head code of the instruction, and hence, a pipeline control unit PCNT invalidates the decoded result of the second instruction decoder ID1. Thus, it is permitted to decode the two shortest instructions in parallel, and to eliminate the erroneous information of the decoded result of the second decoder in the case of the fetch of the non-shortest instruction.

Abstract: A data processor in which, when two primitive instructions are decoded by instruction decoders, a microprogram ROM is not used under the control of a selector, and the two primitive instructions are executed in parallel by instruction execution units in accordance with the decoded outputs of the instruction decoders. When a high performance instruction is decoded by one of the instruction decoders, at a first step processing, one of the instruction execution units selects the output of the one instruction decoder to execute the instruction. At a second step processing, the one instruction execution unit selects a microinstruction of the microprogram ROM and executes the instruction. It is therefore unnecessary to use the microprogram ROM for the execution of a primitive instruction and a high performance instruction at the first step processing, thereby reducing the capacity, area and power consumption of the microprogram ROM.

Abstract: An input apparatus capable of concurrently accommodating itself to any external signal from a different hydraulic control system or the like. The apparatus includes electrical load sensors each arranged on a push rod or block for detecting the amount of operation of a control lever to generate an electrical signal corresponding to the amount of operation of the control lever. Also, an input apparatus which is capable of concurrently responding to both a signal generated by itself and an external signal fed thereto is provided. The apparatus includes a pilot section for exerting force which permits a shuttle to be moved against coiled compression springs. The pilot section is fed with a signal from an external hydraulic control system.

Abstract: A data processor is provided with a first register storing a first half word of one instruction; a second register storing a second half word of the instruction; a first decoder decoding the first half word and at the same time detecting whether there exists an addressing extension portion between the first half word and the second half word; a second decoder decoding the second half word; and, a decode result generating circuit, to which a detection signal of the first decoder indicates whether the addressing extension portion exists. A decode result of the first decoder and a decode result of the second decoder are supplied to the decode result generating circuit. An extension portion register is provided to store the addressing extension portion. When the first decoder detects the addressing extension portion, the decode result generating circuit invalidates the decode result of the second decoder.

Abstract: An input apparatus capable of concurrently accommodating itself to any external signal from a different hydraulic control system or the like. The apparatus includes electrical load sensors each arranged on a push rod or block for detecting the amount of operation of a control lever to generate an electrical signal corresponding to the amount of operation of the control lever. Also, an input apparatus which is capable of concurrently responding to both a signal generated by itself and an external signal fed thereto is provided. The apparatus includes a pilot section for exerting force which permits a shuttle to be moved against coiled compression springs. The pilot section is fed with a signal from an external hydraulic control system.

Abstract: In a pipeline processing microprocessor, an instruction fetch unit is keyed to the formation or nonformation of a conditional branch micro-instruction result to determine the subsequent macro-instruction to be fetched from an external memory or cache. A macro-instruction is first decoded in an instruction decoder to generate micro-addresses which address is a micro-ROM. The first micro-instruction retrieved from the micro-ROM contains information for executing a conditional discrimination, a signal requesting branch ready, and a subsequent micro-address for the actual execution of the branch request in accordance with the result of the conditional discrimination. When the branch condition is satisfied, a micro-address generating circuit feeds the subsequent micro-instruction to a micro-ROM address decoder and the least significant bit of the subsequent micro-address to a micro-address analyzing circuit.