Patents by Inventor Susumu Ono

Susumu Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111029
    Abstract: To provide an optical module that can synchronize a vibration frequency and a swing angle without complicating a system. An optical module including: a double-sided mirror that rotates or undergoes pendulum motion about at least one rotation axis; a plane mirror disposed at an angle of 45 degrees from a horizontal surface on a back surface side of the double-sided mirror; and a uniaxial retroreflective mirror disposed at an angle of 45 degrees from the horizontal surface on a front surface side of the double-sided mirror, in which an axis of retroreflective is perpendicular to the horizontal surface and a normal line of the uniaxial retroreflective mirror.
    Type: Application
    Filed: October 21, 2021
    Publication date: April 4, 2024
    Inventors: TOMOKI ONO, SUSUMU ICHIKAWA, TSUBASA SUGIYAMA
  • Patent number: 11118087
    Abstract: Provided is a film-forming resin composition for protecting an article that an organic polymer is exposed, including a polyurethane resin (A) having a hydroxyl group, a (meth)acrylic resin (B) having a hydroxyl group, and a polyfunctional isocyanate (C), in which the composition has a cross-linking density n of 1.0×10?4 to 5.0×10?3 mol/cm3, which is determined according to Mathematical Formula (1) n=E?min/(3RT). Here, E?min represents a minimum value E?min of storage elastic modulus of a cured film obtained by curing the resin composition at 80° C. for 16 hours in a case where the cured film is subjected to viscoelasticity measurement at a frequency of 1.0 Hz and a temperature range of ?40° C. to 160° C., T represents an absolute temperature at the minimum value E?min, and R represents a gas constant.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: September 14, 2021
    Assignee: NATOCO CO., LTD.
    Inventors: Susumu Ono, Takashi Tanaka, Takafumi Yoshino
  • Publication number: 20210162724
    Abstract: It is an object of the present invention to provide a coating agent composition from which a cured layer superior in water scale resistance and chemical resistance as well as in processability can be obtained. A cured film superior in water scale resistance and chemical resistance as well as in processability can be obtained from a coating agent composition for a laminated film to protect an exterior curved surface of a vehicle, including a component (A1): a (meth)acrylic resin having a hydroxyl group, and a component (B): a polyfunctional isocyanate compound, wherein the component (A1) has an alicyclic structure (a11) and a structure (a12) selected from the group consisting of polylactone, polycarbonate, polyester and polyether, and the component (A1) has a hydroxyl value of 50 to 150 mg KOH/g.
    Type: Application
    Filed: November 24, 2020
    Publication date: June 3, 2021
    Inventor: Susumu ONO
  • Publication number: 20210009856
    Abstract: Provided is a film-forming resin composition for protecting an article that an organic polymer is exposed, including a polyurethane resin (A) having a hydroxyl group, a (meth)acrylic resin (B) having a hydroxyl group, and a polyfunctional isocyanate (C), in which the composition has a cross-linking density n of 1.0×10?4 to 5.0×10?3 mol/cm3, which is determined according to Mathematical Formula (1) n=E?min/(3RT). Here, E?min represents a minimum value E?min of storage elastic modulus of a cured film obtained by curing the resin composition at 80° C. for 16 hours in a case where the cured film is subjected to viscoelasticity measurement at a frequency of 1.0 Hz and a temperature range of ?40° C. to 160° C., T represents an absolute temperature at the minimum value E?min, and R represents a gas constant.
    Type: Application
    Filed: February 13, 2019
    Publication date: January 14, 2021
    Inventors: Susumu ONO, Takashi TANAKA, Takafumi YOSHINO
  • Patent number: 10115563
    Abstract: An electron-beam lithography method includes, computing and outputting a development time of a positive-tone electron-sensitive layer and a parameter recipe of an electron-beam device by using a pattern dimension simulation system, performing a low-temperature treatment to chill a developer solution, utilizing an electron-beam to irradiate an exposure region of the positive-tone electron-sensitive layer based on the parameter recipe, and utilizing the chilled developer solution to develop a development region of the positive-tone electron-sensitive layer based on the development time. The development region is present within the exposure region, and an area of the exposure region is smaller than that of the first portion. As a result, the electron-beam lithography method may control a dimension of a development pattern of the positive-tone electron-sensitive layer more accurately, and may also shrink a minimum dimension of the development pattern of the positive-tone electron-sensitive layer.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: October 30, 2018
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Chieh-Hsiung Kuan, Chun Nien, Wen-Sheng Su, Li-Cheng Chang, Cheng-Huan Chung, Wei-Cheng Rao, Hsiu-Yun Yeh, Shao-Wen Chang, Kuan-Yuan Shen, Susumu Ono
  • Publication number: 20180149980
    Abstract: An electron-beam lithography method includes, computing and outputting a development time of a positive-tone electron-sensitive layer and a parameter recipe of an electron-beam device by using a pattern dimension simulation system, performing a low-temperature treatment to chill a developer solution, utilizing an electron-beam to irradiate an exposure region of the positive-tone electron-sensitive layer based on the parameter recipe, and utilizing the chilled developer solution to develop a development region of the positive-tone electron-sensitive layer based on the development time. The development region is present within the exposure region, and an area of the exposure region is smaller than that of the first portion. As a result, the electron-beam lithography method may control a dimension of a development pattern of the positive-tone electron-sensitive layer more accurately, and may also shrink a minimum dimension of the development pattern of the positive-tone electron-sensitive layer.
    Type: Application
    Filed: June 1, 2017
    Publication date: May 31, 2018
    Inventors: Chieh-Hsiung KUAN, Chun NIEN, Wen-Sheng SU, Li-Cheng CHANG, Cheng-Huan CHUNG, Wei-Cheng RAO, Hsiu-Yun YEH, Shao-Wen CHANG, Kuan-Yuan SHEN, Susumu ONO
  • Publication number: 20180115760
    Abstract: A sound and video processing system includes: a display, having a rectangular display region, that displays a video image in a circular video-image display region smaller than the rectangular display region; and a sound collector that collects sound. A processor generates emphasized audio data, in which sound is emphasized in at least one direction from a position of the sound collector toward at least one position corresponding to at least one designated location in the video image. In response to receiving designation outside the video-image display region, the processor displays a state display area or an adjustment operation area for the sound to be output from the speaker in a rectangular region which has a diagonal line extending from one of four corners of the rectangular display region to a center of the video-image display region and intersecting with a boundary line of the video-image display region.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 26, 2018
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LT D.
    Inventors: Hirotaka SAWA, Shinichi SHIGENAGA, Toshimichi TOKUDA, Shintaro YOSHIKUNI, Shuichi WATANABE, Tadashi MAKI, Hirokazu TASAKA, Susumu ONO, Keisuke FUJIMOTO, Shojiro MATSUO, Teppei FUKUDA, Hiroyuki MATSUMOTO, Akitoshi IZUMI, Hisashi TSUJI, Kazunori HAYASHI, Ryoichi YUGE
  • Publication number: 20180115759
    Abstract: A sound and video processing system includes: a display that displays a video image captured by the camera; a sound collector that collects sound; an input device that receives designation of at least one designated location in the video image displayed on the display. A processor generates emphasized audio data, in which sound is emphasized in at least one direction from a position of the sound collector toward at least one position corresponding to the at least one designated location. The processor displays at least one identification shape at the at least one designated location. In response to receiving re-designation of one of the at least one designated location by the input device, the processor outputs audio data in which emphasis of sound stops in a direction from the position of the sound collector toward the position corresponding to the re-designated location.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 26, 2018
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hirotaka SAWA, Shinichi SHIGENAGA, Toshimichi TOKUDA, Shintaro YOSHIKUNI, Shuichi WATANABE, Tadashi MAKI, Hirokazu TASAKA, Susumu ONO, Keisuke FUJIMOTO, Shojiro MATSUO, Teppei FUKUDA, Hiroyuki MATSUMOTO, Akitoshi IZUMI, Hisashi TSUJI, Kazunori HAYASHI, Ryoichi YUGE
  • Patent number: 9826211
    Abstract: A recorder receives designation of a video which is desired to be reproduced from a user. If designation of one or more designated locations where sound is emphasized on a screen of a display which displays the video is received by the recorder from the user via an operation unit during reproduction or temporary stopping of the video, a signal processing unit performs an emphasis process on audio data, that is, the signal processing unit emphasizes audio data in directions directed toward positions corresponding to the designated locations from a microphone array by using audio data recorded in the recorder. A reproducing device reproduces the emphasis-processed audio data and video data in synchronization with each other.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 21, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hirotaka Sawa, Shinichi Shigenaga, Toshimichi Tokuda, Shintaro Yoshikuni, Shuichi Watanabe, Tadashi Maki, Hirokazu Tasaka, Susumu Ono, Keisuke Fujimoto, Shojiro Matsuo, Teppei Fukuda, Hiroyuki Matsumoto, Akitoshi Izumi, Hisashi Tsuji, Kazunori Hayashi, Ryoichi Yuge
  • Publication number: 20150350621
    Abstract: A recorder receives designation of a video which is desired to be reproduced from a user. If designation of one or more designated locations where sound is emphasized on a screen of a display which displays the video is received by the recorder from the user via an operation unit during reproduction or temporary stopping of the video, a signal processing unit performs an emphasis process on audio data, that is, the signal processing unit emphasizes audio data in directions directed toward positions corresponding to the designated locations from a microphone array by using audio data recorded in the recorder. A reproducing device reproduces the emphasis-processed audio data and video data in synchronization with each other.
    Type: Application
    Filed: December 27, 2013
    Publication date: December 3, 2015
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hirotaka SAWA, Shinichi SHIGENAGA, Toshimichi TOKUDA, Shintaro YOSHIKUNI, Shuichi WATANABE, Tadashi MAKI, Hirokazu TASAKA, Susumu ONO, Keisuke FUJIMOTO, Shojiro MATSUO, Teppei FUKUDA, Hiroyuki MATSUMOTO, Akitoshi IZUMI, Hisashi TSUJI, Kazunori HAYASHI, Ryoichi YUGE
  • Patent number: 8378554
    Abstract: A multi-layer piezoelectric element of high durability wherein external electrodes do not peel off the surface of a stack even when operated continuously over a long period of time under a high electric field and a high pressure, a method for manufacturing the same and an injection apparatus using the same are provided. The multi-layer piezoelectric element comprises a stack 10 consisting of a plurality of piezoelectric layers 1 and a plurality of metal layers 2 which are stacked alternately one on another and external electrodes (covering member) 4 that cover at least a part of the side faces of the stack 10, wherein at least one metal layer 2a among the plurality of metal layers 2 is a porous metal layer 2a which has more voids than the metal layers 2b that adjoin the metal layer 2a on both sides thereof in the stacking direction, and a part of the external electrodes 4 infiltrates between two piezoelectric layers 1, 1 which adjoin the porous metal layer 2a in the stacking direction.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: February 19, 2013
    Assignee: Kyocera Corporation
    Inventors: Shigenobu Nakamura, Susumu Ono, Takeshi Kato, Koichi Nagasaki
  • Patent number: 8104693
    Abstract: A multilayer piezoelectric element is provided which has excellent durability even if it is continuously driven for a long period of time under high temperature and high humidity. The multilayer piezoelectric element has a laminated body that a plurality of piezoelectric layers are laminated through an internal electrode interposed therebetween, in which the internal electrode, a dummy electrode spaced apart and electrically insulated from the internal electrode, and an insulating part between the dummy electrode and the internal electrode are arranged between two adjacent piezoelectric layers. A porous part having a larger number of voids than the internal electrode is formed at positions opposed in the laminating direction to the internal electrode, the dummy electrode and the insulating part through the piezoelectric layer interposed therebetween, respectively.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: January 31, 2012
    Assignee: Kyocera Corporation
    Inventor: Susumu Ono
  • Publication number: 20100282874
    Abstract: A multi-layer piezoelectric element of high durability wherein external electrodes do not peel off the surface of a stack even when operated continuously over a long period of time under a high electric field and a high pressure, a method for manufacturing the same and an injection apparatus using the same are provided. The multi-layer piezoelectric element comprises a stack 10 consisting of a plurality of piezoelectric layers 1 and a plurality of metal layers 2 which are stacked alternately one on another and external electrodes (covering member) 4 that cover at least a part of the side faces of the stack 10, wherein at least one metal layer 2a among the plurality of metal layers 2 is a porous metal layer 2a which has more voids than the metal layers 2b that adjoin the metal layer 2a on both sides thereof in the stacking direction, and a part of the external electrodes 4 infiltrates between two piezoelectric layers 1, 1 which adjoin the porous metal layer 2a in the stacking direction.
    Type: Application
    Filed: October 26, 2006
    Publication date: November 11, 2010
    Applicant: KYOCERA CORPORATION
    Inventors: Shigenobu Nakamura, Susumu Ono, Takeshi Kato, Koichi Nagasaki
  • Publication number: 20100072306
    Abstract: A multilayer piezoelectric element is provided which has excellent durability even if it is continuously driven for a long period of time under high temperature and high humidity. The multilayer piezoelectric element has a laminated body that a plurality of piezoelectric layers are laminated through an internal electrode interposed therebetween, in which the internal electrode, a dummy electrode spaced apart and electrically insulated from the internal electrode, and an insulating part between the dummy electrode and the internal electrode are arranged between two adjacent piezoelectric layers. A porous part having a larger number of voids than the internal electrode is formed at positions opposed in the laminating direction to the internal electrode, the dummy electrode and the insulating part through the piezoelectric layer interposed therebetween, respectively.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 25, 2010
    Applicant: KYOCERA CORPORATION
    Inventor: Susumu Ono
  • Publication number: 20100066211
    Abstract: In order to provide a multi-layer electronic component in which the occurrence of delamination between the ceramic layer and the internal electrode is restricted and a method for manufacturing the same, the multi-layer electronic component of the present invention comprises a stack formed by stacking piezoelectric layers and internal electrodes one on another alternately and a pair of external electrodes formed on two opposing side faces of the stack, wherein the internal electrode consists of a first internal electrode connected to the external electrode formed on one of the two side faces and a second internal electrode located between the first internal electrode and connected to the external electrode formed on the other one of the two side faces, and wherein the internal electrodes and the piezoelectric layers are faced in proximity so that a space between them is 2 ?m or less over an area occupying 50% or more of the active region where the first internal electrode and the second internal electrode oppo
    Type: Application
    Filed: October 28, 2009
    Publication date: March 18, 2010
    Applicant: KYOCERA CORPORATION
    Inventors: Susumu ONO, Takeshi OKAMURA, Katsushi SAKAUE, Takaaki HIRA, Masaki TERAZONO
  • Patent number: 7633210
    Abstract: In order to provide a multi-layer electronic component in which the occurrence of delamination between the ceramic layer and the internal electrode is restricted and a method for manufacturing the same, the multi-layer electronic component of the present invention comprises a stack formed by stacking piezoelectric layers and internal electrodes one on another alternately and a pair of external electrodes formed on two opposing side faces of the stack, wherein the internal electrode consists of a first internal electrode connected to the external electrode formed on one of the two side faces and a second internal electrode located between the first internal electrode and connected to the external electrode formed on the other one of the two side faces, and wherein the internal electrodes and the piezoelectric layers are faced in proximity so that a space between them is 2 ?m or less over an area occupying 50% or more of the active region where the first internal electrode and the second internal electrode oppo
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: December 15, 2009
    Assignee: Kyocera Corporation
    Inventors: Susumu Ono, Takeshi Okamura, Katsushi Sakaue, Takaaki Hira, Masaki Terazono
  • Publication number: 20070069610
    Abstract: In order to provide a multi-layer electronic component in which the occurrence of delamination between the ceramic layer and the internal electrode is restricted and a method for manufacturing the same, the multi-layer electronic component of the present invention comprises a stack formed by stacking piezoelectric layers and internal electrodes one on another alternately and a pair of external electrodes formed on two opposing side faces of the stack, wherein the internal electrode consists of a first internal electrode connected to the external electrode formed on one of the two side faces and a second internal electrode located between the first internal electrode and connected to the external electrode formed on the other one of the two side faces, and wherein the internal electrodes and the piezoelectric layers are faced in proximity so that a space between them is 2 ?m or less over an area occupying 50% or more of the active region where the first internal electrode and the second internal electrode oppo
    Type: Application
    Filed: July 28, 2004
    Publication date: March 29, 2007
    Inventors: Susumu Ono, Takeshi Okamura, Katsushi Sakaue, Takaaki Hira, Masaki Terazono
  • Patent number: 6605811
    Abstract: In an electron beam lithography system, an outputted main signal is applied directly to deflection plates, whereas an outputted auxiliary signal is applied to the deflection plate through a capacitive coupling for writing a wide strip-like pattern accurately at a high speed. In the electron beam lithography system, a deflection signal is divided into a main signal having a low frequency and a large amplitude and an auxiliary signal having a high frequency and a small amplitude. The main signal is applied directly to deflection plates, and the auxiliary signal is applied to the deflection plate through a capacitor.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: August 12, 2003
    Assignee: Elionix Inc.
    Inventors: Masanao Hotta, Yasuhiko Kojima, Takaomi Ito, Katsumi Yokota, Tetsuyuki Okabayashi, Akio Otani, Susumu Ono
  • Publication number: 20030089858
    Abstract: In an electron beam lithography system, an outputted main signal is applied directly to deflection plates, whereas an outputted auxiliary signal is applied to the deflection plate through a capacitive coupling for thereby writing a wide strip-like pattern accurately at a high speed.
    Type: Application
    Filed: November 9, 2001
    Publication date: May 15, 2003
    Inventors: Masanao Hotta, Yasuhiko Kojima, Takaomi Ito, Katsumi Yokota, Tetsuyuki Okabayashi, Akio Otani, Susumu Ono
  • Patent number: 6414417
    Abstract: A laminated piezoelectric actuator comprising external electrodes formed on the side surfaces of an actuator body constituted by plural piezoelectric layers and plural internal electrode layers alternatingly laminated in the direction of height, external electrodes connecting the ends of said internal electrode layers, the internal electrode layers neighboring one another with the piezoelectric layers sandwiched among them of one side constituting first electrode layers and the internal electrode layers of the other side constituting second electrode layers, wherein the external electrodes include a first external electrode connecting the ends of the first electrode layers, and a second external electrode connecting the ends of the second electrode layers and is formed on a side surface of the actuator body different from the side surface on where the first external electrode is formed, insulating blocks are arranged between the first external electrode and the ends of the second electrode layers, and between
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: July 2, 2002
    Assignee: Kyocera Corporation
    Inventors: Hirotaka Tsuyoshi, Hideki Uchimura, Shigenobu Nakamura, Susumu Ono