Abstract: An embodiment of manufacturing method of a flat-panel display device having a display panel and a transparent protector sheet; comprises: setting a bi-directionally Y-shape branched line pattern within a rectangular to-be-bonded area, which is formed of two Y-shaped intersections of a center line and angle bisector lines of the corners, of the to-be-bonded area; and applying adhesive resin onto the protector sheet or onto the display panel by forming circular or ellipsoidal dot patterns of applied adhesive resin so that: the dot patterns are arranged on the center-line segment and on the branch lines or their vicinities; and the dot patterns are arranged in symmetry with respect to the center line and to its perpendicular bisector.

Abstract: An embodiment of manufacturing method of a flat-panel display device having a display panel and a transparent protector sheet; comprises: applying of adhesive resin onto the transparent protector sheet or the display panel to form dot patterns of applied adhesive resin; seizing the protector sheet and the display panel on upper and lower chucking parts; colliding of undermost tip of the applied resin onto the panel or the protector sheet at an approaching rate no more than a predetermined rate, preferably in a range of 0.01-0.5 mm/sec; and squeezing of the layer by moving the upper or lower chucking part at a rate no less than three times of the approaching rate at a time of the colliding, preferably in a range of 1-10 mm/sec.

Abstract: An embodiment of manufacturing method of a flat-panel display device having a display panel and a transparent protector sheet; comprises: setting a bi-directionally Y-shape branched line pattern within a rectangular to-be-bonded area, which is formed of two Y-shaped intersections of a center line and angle bisector lines of the corners, of the to-be-bonded area; and applying adhesive resin onto the protector sheet or onto the display panel by forming circular or ellipsoidal dot patterns of applied adhesive resin so that: the dot patterns are arranged on the center-line segment and on the branch lines or their vicinities; and the dot patterns are arranged in symmetry with respect to the center line and to its perpendicular bisector.

Abstract: An embodiment of manufacturing method of a flat-panel display device having a display panel and a transparent protector sheet; comprises: applying of adhesive resin onto the transparent protector sheet or the display panel to form dot patterns of applied adhesive resin; seizing the protector sheet and the display panel on upper and lower chucking parts; colliding of undermost tip of the applied resin onto the panel or the protector sheet at an approaching rate no more than a predetermined rate, preferably in a range of 0.01-0.5 mm/sec; and squeezing of the layer by moving the upper or lower chucking part at a rate no less than three times of the approaching rate at a time of the colliding, preferably in a range of 1-10 mm/sec.

Abstract: A remote ground terminal transmitter for transmitting a modulated data signal having a constant envelope amplitude. The remote ground terminal transmitter comprises a source of data signals, a modulator for providing a carrier signal, receiving a data signal from the source of data signals, and modulating the carrier signal with the received data signal so as to produce a constant envelope minimum shift key modulation signal. The transmitter further comprises a power amplifier which operates in the saturation mode to amplify the modulated carrier signal produced by the modulator to the desired power level.

Abstract: For spectrum spreading with a small spreading factor N which may be four, an input bit sequence of an input bit rate fs is eventually converted into a serial data sequence of serial data of which each serial datum consists of N repetitions of N consecutive bits of the input bit sequence. By a shift register (19) operable at fs and a memory (23) operable at fs/4, the input bit sequence is first converted into N parallel bit sequences, which are converted into the serial data sequence by a selector (27) operable at Nfs.

Abstract: An intermittently transmitted burst modulation signal is demodulated to a baseband signal and multiplied with a variable gain coefficient. A range where a difference signal of a power signal of the multiplied signal from a reference power level is included, in a plurality of level ranges, is decided. A loop constant is determined in accordance with the decided range and is multiplied with the difference signal. An integrated multiplied difference signal with the loop constant is used for changing the variable gain constant.

Abstract: A time division PLL is composed of a complex multiplier (1), a phase difference detector (2), a low-pass filter (3), an adder (4) and a digital VCO (5). A D.C. value indicating the recovered carrier component of a receive burst is obtained by a squaring circuit (9) from a baseband signal, which is the output of the complex multiplier (1). The time division PLL operates as a PLL having frequency different lead-in ranges on a time division basis, differing between the period in which no burst has been received yet and the period in which the former part of the carrier recovery section of the receive burst is being received. It operates, from the latter part of the carrier recovery section until the completion of data reception, as a PLL having the frequency pull-in range in which the greatest D.C. value was outputted during the time division operation.

Abstract: A satellite packet communication system comprising a central station and VSAT stations. The central station generates chip-rate clock pulses and transmits a series of data on timeslots of a frame to a satellite transponder, and a plurality of terminal stations. Each VSAT station receives the frame from the transponder and recovers the chip-rate clock pulses from the received frame. A pseudorandom number (PN) sequence generator, provided in the terminal station is synchronized with the recovered chip-rate clock pulses for generating bits of a PN sequence with which packetized data bits are pseudorandomly modulated and transmitted in burst form to the transponder. The central station includes a correlator which is synchronized with the central station's chip-rate clock pulses to detect correlations between the pseudorandomly modulated data bits a sequence of pseudorandom numbers corresponding to the PN sequence bits of the terminal stations.

Abstract: In a coherent M-ary PSK demodulator, an M-ary PSK detector demodulates a received M-ary PSK modulated convolutional code with a carrier recovered by a voltage-controlled oscillator to produce first and second channels of demodulated convolutional codes. A convolutional decoder decodes the signals of the first and second channels while correcting bit errors. An error rate detector is provided for detecting when the number of such errors occurring during a specified period of time is smaller than a predetermined value and generates a signal indicating that the convolutional decoder is synchronized with the demodulated signals. The power levels of signal and noise components of the demodulated channels are detected by a power detector.

Abstract: Supplied with an input signal into which a carrier signal is modulated at a frame period by a data signal and unique words periodically interspersed throughout the data signal, a demodulating circuit (16) quadrature demodulates the input signal into an output signal. A cross-correlating circuit (23) calculates a cross-correlation coefficient between the output signal and a locally known unique word. A frame synchronizing circuit (24) compares the cross-correlation coefficient with a predetermined threshold value and delivers an aperture when the cross-correlation coefficient is below the predetermined threshold value. A phase calculating circuit (25) calculates phase errors between a recovered carrier signal recovered from the output signal and a regenerated carrier signal which is a correct reproduction of the carrier signal. The phase errors are set in a carrier regenerating circuit (17) to render the recovered carrier signal identical with the regenerated carrier signal at the aperture interval.

Abstract: A synchronization (sync) word detection apparatus which, on receiving a signal in which a sync word having a predetermined length (N) is inserted beforehand, detects the sync word out of a demodulated and soft-decided sequence of the received signal. A cross correlator (4) calculates a cross correlation value of the soft-decided and demodulated sequence fed thereto and the sync word. A threshold generating section (1, 2, 3) determines a means power of the demodulated and soft-decided sequence and generates a threshold value on the basis of the mean power. A comparing circuit (5) produces a detection signal when the cross correlation exceeds the threshold value. The apparatus reduces the false detection probability and misdetection prbability even when the receive field intensity sharply changes on a transmission path.

Abstract: An apparatus for detecting burst signals used in satellite communication, for example, detects burst signals of the type comprising a unique word followed by a series of data. The burst signals are of the type that have undergone cyclic redundancy check (CRC) coding and error-correction coding. A unique word detector detects the unique word in the burst signal. An error-correcting decoder decodes the error-correction code used with the data. Two forms of error detection are used to reduce the possibility of erroneous data being mistakenly considered error-free. A cyclic redundancy check error detector detects any CRC error in the decoded data. A channel quality detector detects quality of the channel on which the burst signal is received. An output circuit provides an output signal indicating presence or absence of error in the data in response to outputs of the unique word detector, the CRC error detector, and the channel quality detector.

Abstract: In a variable bit rate clock recovery circuit, a phase difference between an input demodulated signal and a recovered clock signal is detected, the detected phase difference signal is filtered by a loop filter and is then integrated, the integrated signal is supplied as an address to first and second ROMs, which store data of cosine and sine waves in advance, output data from the first and second ROMs are respectively D/A-converted by first and second D/A converters, an output signal from a variable frequency generator is modulated by using an output from the first D/A converter, a signal obtained by shifting the output signal from the variable frequency signal generator by .pi./2 radians is modulated by an output from the second D/A converter, and the respective modulated signals are synthesized, thereby obtaining a reference clock signal.

Abstract: A carrier recovery circuit comprises a voltage-controlled oscillator with a .pi./2 phase shifter coupled to it for generating carriers of quadrature phase relationship. First and second phase comparators respectively detect phase differences between an offset QPSK modulated signal and the carriers of the quadrature phase relationship. Signal from the first phase comparator is delayed by a 1/2 symbol duration and applied to one input of a quadri-phase detector having stable phase angles at .pi./4, (3/4).pi., (5/4).pi. and (7/4).pi. radian and signal from the second phase comparator is applied to the other input of the quadri-phase detector. A bit timing recovery field (1010 . . . 1010) of the second channel is detected from the output of the second phase comparator. Signal from the quadri-phase detector is applied to a loop filter and thence to the voltage-controlled oscillator during the time when a bit timing recovery field (BTR) of the second channel is not still detected.

Abstract: In a phase controlled demodulator, a modulated digital input signal is demodulated into quadrature signals with a carrier recovered by a voltage controlled oscillator. A phase difference between the quadrature signals is detected by a phase detector of Costas loop and applied through a loop filter to the voltage controlled oscillator to control the frequency and phase of the recovered carrier when the frequency deviation between the received and recovered carriers is within a phase control range. When the frequency deviation exceeds the phase control range, the output of the phase detector is a beat of the two carriers and a frequency sweep control voltage is applied to the VCO to search for the missing carrier. The magnitude of the beat is detected and compared with a predetermined threshold value.

Abstract: A carrier-to-noise detector comprises an A/D converter (1) which samples an output of the demodulator of a digital transmission system at a symbol clock rate and converting it to a digital signal having positive and negative values. An absolute value converting circuit (2) converts the output of A/D converter into an absolute value which is averaged by a first averaging circuit (3) over a period sufficient to suppress short term variations and then squared by a first squaring circuit (4) to give an output representing the carrier component. The output of A/D converter is, on the other hand, squared by a second squaring circuit (5) and averaged by a second averaging circuit (6) to suppress short term variations to give an output representing a total of the carrier and noise components. The carrier component in the output of the second averaging circuit 6 is subtracted by a subtractor (7).

Abstract: A carrier wave recovery system for a slotted ALOHA system is disclosed. In a time slot where a burst is not inputted, the frequency of oscillator means is locked to a mean value of carrier wave frequencies of bursts which were received in the past, thereby allowing a minimum of initial frequency offset to occur. A voltage controlled oscillator frequency is controlled at initial pull-in to an average frequency of the highest and lowest carrier wave frequencies of an input burst signal.

Abstract: A carrier recovery circuit comprises first and second mixers for mixing a received PSK signal with first and second reference frequency signals. A remodulator extracts a preamble from each burst of the PSK signal and supplies the extracted carrier to a carrier recovery means to cause it to derive a reference carrier from the extracted preamble. A phase detector is connected to the outputs of the first and second mixers for detecting a phase difference between the PSK signal and the reference carrier, the detected phase difference being applied to a resettable noise reduction circuit for reducing amplitude fluctuations contained in the phase difference, the noise reduction circuit being arranged to be reset in response to each of the bursts to discharge energy stored as a result of the noise reduction and eliminate interburst phase errors which occur as a result of interburst frequency variations.

Abstract: In a time division multiple access communication system including a nonlinear signal processing element, an accurate carrier power-to-noise ratio is obtained by the circuit of the present invention. In the inventive circuit, noise power is determined solely by the quadrature noise and, hence, is free from measurement errors caused by the compression of in-phase noise associated with a non-linear element in the transmission channel.