Patents by Inventor Susumu Ozawa

Susumu Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8083267
    Abstract: Each of ridges 7 on respective opposite side surfaces of a gasket 4 has a trapezoidal cross sectional shape defined by an outer tapered face 7a providing an outer peripheral surface, an inner tapered face 7b providing an inner peripheral surface and a flat face 7c providing a top end surface. The hardness of the gasket 4, the angle between the tapered faces 7a, 7b of the ridge 7, the height of the ridge 7 and the area of the flat top end face 7c of the ridge are so determined that the value of thrust for tightening up the coupling is between a predetermined minimum value and a predetermined maximum value.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: December 27, 2011
    Assignee: Fujikin Incorporated
    Inventors: Shigeru Itoi, Michio Yamaji, Tsutomu Shinohara, Kenji Tsubota, Tadanobu Yoshida, Susumu Ozawa
  • Publication number: 20110026301
    Abstract: According to one embodiment, a semiconductor memory device includes first select line groups laminated in a vertical direction, and each including first select lines extending in a first direction, second select line groups alternately laminated with the first select line groups, and each including second select lines extending in a second direction that intersects with the first direction, and memory cells arranged between the first select lines and the second select lines. Even-numbered layers and odd-numbered layers of the first select line groups are arranged to be shifted in the second direction.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 3, 2011
    Inventor: Susumu Ozawa
  • Patent number: 7754512
    Abstract: According to the present invention, a light-emitting semiconductor device has light-emitting elements separated by isolation trenches, preferably on two sides of each light-emitting element. The device may be fabricated by forming a single band-shaped diffusion region, then forming trenches that divide the diffusion region into multiple regions, or by forming individual diffusion regions and then forming trenches between them. The trenches prevent overlap between adjacent light-emitting elements, regardless of their junction depth, enabling a high-density array to be fabricated while maintaining adequate junction depth.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: July 13, 2010
    Assignee: Oki Data Corporation
    Inventors: Masumi Taninaka, Hiroyuki Fujiwara, Susumu Ozawa, Masaharu Nobori
  • Publication number: 20090015010
    Abstract: Each of ridges 7 on respective opposite side surfaces of a gasket 4 has a trapezoidal cross sectional shape defined by an outer tapered face 7a providing an outer peripheral surface, an inner tapered face 7b providing an inner peripheral surface and a flat face 7c providing a top end surface. The hardness of the gasket 4, the angle between the tapered faces 7a, 7b of the ridge 7, the height of the ridge 7 and the area of the flat top end face 7c of the ridge are so determined that the value of thrust for tightening up the coupling is between a predetermined minimum value and a predetermined maximum value.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 15, 2009
    Applicant: FUJIKIN INCORPORATED
    Inventors: Shigeru Itoi, Michio Yamaji, Tsutomu Shinohara, Kenji Tsubota, Tadanobu Yoshida, Susumu Ozawa
  • Publication number: 20060055122
    Abstract: Each of ridges 7 on respective opposite side surfaces of a gasket 4 has a trapezoidal cross sectional shape defined by an outer tapered face 7a providing an outer peripheral surface, an inner tapered face 7b providing an inner peripheral surface and a flat face 7c providing a top end surface.
    Type: Application
    Filed: October 31, 2003
    Publication date: March 16, 2006
    Applicant: Fujikin Incorporated
    Inventors: Shigeru Itoi, Michio Yamaji, Tsutomu Shinohara, Kenji Tsubota, Tadanobu Yoshida, Susumu Ozawa
  • Publication number: 20050189547
    Abstract: According to the present invention, a light-emitting semiconductor device has light-emitting elements separated by isolation trenches, preferably on two sides of each light-emitting element. The device may be fabricated by forming a single band-shaped diffusion region, then forming trenches that divide the diffusion region into multiple regions, or by forming individual diffusion regions and then forming trenches between them. The trenches prevent overlap between adjacent light-emitting elements, regardless of their junction depth, enabling a high-density array to be fabricated while maintaining adequate junction depth.
    Type: Application
    Filed: May 3, 2005
    Publication date: September 1, 2005
    Inventors: Masumi Taninaka, Hiroyuki Fujiwara, Susumu Ozawa, Masaharu Nobori
  • Patent number: 6909122
    Abstract: According to the present invention, a light-emitting semiconductor device has light-emitting elements separated by isolation trenches, preferably on two sides of each light-emitting element. The device may be fabricated by forming a single band-shaped diffusion region, then forming trenches that divide the diffusion region into multiple regions, or by forming individual diffusion regions and then forming trenches between them. The trenches prevent overlap between adjacent light-emitting elements, regardless of their junction depth, enabling a high-density array to be fabricated while maintaining adequate junction depth.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: June 21, 2005
    Assignee: Oki Data Corporation
    Inventors: Masumi Taninaka, Hiroyuki Fujiwara, Susumu Ozawa, Masaharu Nobori
  • Patent number: 6781246
    Abstract: An array of semiconductor circuit elements such as light-emitting elements includes a semiconductor layer partially covered by a dielectric film. A first interconnecting pad such as a wire-bonding pad is electrically coupled by conductive paths passing through the semiconductor layer to electrodes of a first group of semiconductor circuit elements formed in the semiconductor layer. A second interconnecting pad such as a wire-bonding pad, formed on the dielectric film, is electrically coupled to electrodes of a second group of semiconductor circuit elements formed in the semiconductor layer by conductive paths insulated from the semiconductor layer by the dielectric film. The second conductive paths cross the first conductive paths at points at which the first conductive paths pass through the semiconductor layer, so that only a single layer of metal interconnecting lines is needed.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: August 24, 2004
    Assignee: Oki Data Corporation
    Inventors: Hiroyuki Fujiwara, Masumi Taninaka, Susumu Ozawa, Masumi Koizumi
  • Publication number: 20040021146
    Abstract: An array of semiconductor circuit elements such as light-emitting elements includes a semiconductor layer partially covered by a dielectric film. A first interconnecting pad such as a wire-bonding pad is electrically coupled by conductive paths passing through the semiconductor layer to electrodes of a first group of semiconductor circuit elements formed in the semiconductor layer. A second interconnecting pad such as a wire-bonding pad, formed on the dielectric film, is electrically coupled to electrodes of a second group of semiconductor circuit elements formed in the semiconductor layer by conductive paths insulated from the semiconductor layer by the dielectric film. The second conductive paths cross the first conductive paths at points at which the first conductive paths pass through the semiconductor layer, so that only a single layer of metal interconnecting lines is needed.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 5, 2004
    Inventors: Hiroyuki Fujiwara, Masumi Taninaka, Susumu Ozawa, Masumi Koizumi
  • Publication number: 20030183831
    Abstract: According to the present invention, a light-emitting semiconductor device has light-emitting elements separated by isolation trenches, preferably on two sides of each light-emitting element. The device may be fabricated by forming a single band-shaped diffusion region, then forming trenches that divide the diffusion region into multiple regions, or by forming individual diffusion regions and then forming trenches between them. The trenches prevent overlap between adjacent light-emitting elements, regardless of their junction depth, enabling a high-density array to be fabricated while maintaining adequate junction depth.
    Type: Application
    Filed: February 27, 2003
    Publication date: October 2, 2003
    Inventors: Masumi Taninaka, Hiroyuki Fujiwara, Susumu Ozawa, Masaharu Nobori
  • Patent number: 6515309
    Abstract: An LED array chip comprises a semiconductor substrate having a front surface and a side surface. The first surface and the front surface come together at an end of the chip to define an end portion of said semiconductor substrate that has an acute angle between the first surface and the front surface. The end of the chip defines an outermost dimension of the chip. The first surface extends further away from the front surface than the diffuison depth of the light emitting elements. A method of manufacturing an LED array chip includes the steps of: forming grooves between adjacent LED arrays of the plurality of LED arrays, each of the grooves having opposing side walls each of which makes an acute angle with the front surface; and dicing the semiconductor wafer except for the opposing side walls of each of the grooves to separate the plurality of LED arrays into individual LED array chips.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: February 4, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hiroshi Tohyama, Susumu Ozawa, Yuko Kasamura, Satoru Yamada
  • Patent number: 6483772
    Abstract: A specifying circuit specifies either the first masking method or the second masking method. A first generation circuit generates a signal corresponding to the first method. A second generation circuit generates a signal corresponding to the second method. A third generation circuit generates a write pulse signal on the basis of the output signal of the first generation circuit in response to the specification of the first masking method made by the specifying circuit and on the basis of the output signal of the second generation circuit in response to the specification of the second masking method made by the specifying circuit.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: November 19, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Susumu Ozawa, Shigeo Ohshima, Katsumi Abe
  • Patent number: 6433367
    Abstract: A semiconductor device has a first surface with at least one wire bonding pad, a second surface located opposite to the first surface, and at least one side sloping inward from the first surface to the second surface. According to a first aspect of the invention, all wire bonding pads formed on the first surface are formed in the part opposite the second surface, so that mechanical loads applied during wire bonding are transmitted to the second surface and do not cause cracks in the sloping side. According to a second aspect of the invention, when an array of such semiconductor devices is mounted on a substrate, resin mounds supporting the sloping sides are formed between the semiconductor devices, so that mechanical loads transmitted to the sloping sides during wire bonding are then transmitted through the resin mounds to the substrate.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: August 13, 2002
    Assignee: Oki Data Corporation
    Inventors: Hiroshi Tohyama, Susumu Ozawa, Satoru Yamada
  • Publication number: 20020031020
    Abstract: A specifying circuit specifies either the first masking method or the second masking method. A first generation circuit generates a signal corresponding to the first method. A second generation circuit generates a signal corresponding to the second method. A third generation circuit generates a write pulse signal on the basis of the output signal of the first generation circuit in response to the specification of the first masking method made by the specifying circuit and on the basis of the output signal of the second generation circuit in response to the specification of the second masking method made by the specifying circuit.
    Type: Application
    Filed: September 12, 2001
    Publication date: March 14, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Susumu Ozawa, Shigeo Ohshima, Katsumi Abe
  • Patent number: 6163501
    Abstract: A synchronous semiconductor memory device comprises: a memory cell array; a decoder circuit for decoding an address, which is supplied in synchronism with a clock, to select a memory cell of the memory cell array; a plurality of main data line pairs, to which data of the memory cell array are transferred; a plurality of data line buffers, each of which is provided in a corresponding one of the main data line pairs and each of which includes a latch circuit; and a plurality of peripheral data lines for transferring data of each of the data line buffers to a data input/output terminal, wherein a plurality of bits of data per data input/output terminal read out of the memory cell array are transferred to the data line buffers via the main data line pairs in parallel, and while head data of the plurality of bits of data pass through the latch circuits to be transferred to one of the peripheral data lines, a plurality of continuous data are temporarily held by the latch circuit, and subsequent data are sequentiall
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: December 19, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeo Ohshima, Susumu Ozawa
  • Patent number: 6158679
    Abstract: An orifice for a pressure-type flow rate controller, which can be produced by a simple method at a low cost, that provides a linearity--between the pressure P1 on the upstream side of the orifice and the flow rate--over a wide range of the pressure ratio P2/P1 of the pressure P2 on the downstream side of the orifice to the upstream pressure P1 and that permits adjustment with ease of flow characteristics among a plurality of orifices. The orifice comprises an inlet taper 1 in the shape of a bugle and a short narrowed straight section 2 adjoining the inlet taper 1, both formed by cutting one opening end of a preliminary hole 6 made in an orifice plate D, and further comprises a short inner taper 3 and an enlarged straight section 4 connecting with the taper 3 which are formed by enlarging the preliminary hole 6 at the other opening end, the short inner taper 3 adjoining the narrowed straight section 2 on one side and neighboring the enlarged straight section 4 on the other side.
    Type: Grant
    Filed: June 16, 1999
    Date of Patent: December 12, 2000
    Assignees: Fujikin Incorporated, Tokyo Electron Ltd., Tadahiro Ohmi
    Inventors: Tadahiro Ohmi, Tetu Kagazume, Kazuhiko Sugiyama, Osamu Fukada, Susumu Ozawa, Yoshihiro Satou, Ryousuke Dohi, Tomio Uno, Kouji Nishino, Hiroyuki Fukuda, Nobukazu Ikeda, Michio Yamaji
  • Patent number: 5745540
    Abstract: A bill counter comprises a case body formed to be a size which can be carried; a display section provided on the surface of the case body; an insertion port provided on one side of the case body which is capable of being expanded/contracted; a taking-out port provided on the other side of the case body; a first feeding-out device which is provided on the insertion port side within the case body and feeds out bills in a bundle inserted to the insertion port by a few sheets; a second feeding-out device which is provided on the taking-out port side within the case body and feeds out bills one by one fed out by the first feeding-out device; a driving section which drives simultaneously the first and the second feeding-out devices; an identifying sensor which identifies bills going toward the taking-out port; and a control section which outputs a signal displaying the number of sheets by unit of each bill and the total amount at least to said display section based on the signal from the identifying sensor and a si
    Type: Grant
    Filed: August 9, 1995
    Date of Patent: April 28, 1998
    Assignee: Mu Co., Ltd.
    Inventors: Hidemi Okada, Susumu Ozawa
  • Patent number: 5035591
    Abstract: A vulcanizing apparatus having penetrating passages connected and communicated with a jacket portion of a mold member. An upper open end portion of one of the penetrating passages is connected to a steam inlet pipe while an upper open end portion of the other penetrating passage is connected to a steam outlet pipe. The connections and communications of the jacket portion with the steam inlet and outlet pipes can be simultaneously and efficiently completed in a single operation. Inner tubes are slidably disposed along the penetrating passages and pressed against the connecting surface of the mold, and appropriate pressure is applied on the seal packing member on the connecting surface independent from the clamping force of the upper mold in order to ensure reliable sealing.
    Type: Grant
    Filed: December 4, 1989
    Date of Patent: July 30, 1991
    Assignees: Sumitomo Rubber Industries, Ltd., Mitsubishi Jukogyo Kabushiki Kaisha
    Inventors: Koji Soeda, Yoshiya Kubota, Shoji Okamoto, Akinori Kubota, Michihito Kobayashi, Masaaki Ijiri, Susumu Ozawa, Kiyoshi Tomosada, Nobuhiko Irie, Akira Hasegawa, Hideaki Katayama, Toshifumi Murakami, Katsuyoshi Sakaguchi
  • Patent number: 4955799
    Abstract: A metal mold centering and clamping device in a tire vulcanizing machine has hydraulic cylinders each having a piston rod equipped with a non-directional bearing at its top portion. The cylinders are mounted on a vulcanizing machine frame close to an outer circumference of a metal mold. An outside portion of a centering member is connected to the vulcanizing machine frame via parallel links to form a parallel linkage, and a bottom portion of the same centering member is connected to the piston rod via a link. On the inside of the centering member and on the outer circumference of a lower metal mold are respectively formed centering surfaces opposed to each other. In addition, at an upper portion of the inside surface of the centering member is formed a clamp claw adapted to be engaged with the edge of the lower metal mold.
    Type: Grant
    Filed: November 9, 1989
    Date of Patent: September 11, 1990
    Assignees: Mitsubishi Jukogyo Kabushiki Kaisha, Sumitomo Rubber Industries, Ltd.
    Inventors: Hideaki Katayama, Toshifumi Murakami, Koji Soeda, Yoshiya Kubota, Shoji Okamoto, Akinori Kubota, Michihito Kobayashi, Masaaki Ijiri, Susumu Ozawa, Kiyoshi Tomosada
  • Patent number: 4840290
    Abstract: A coin exchanging machine has a coin case disposed at the bottom of a casing for accommodating a plurality of coin bundles, a coin pushing mechanism for pushing laterally a row of coin bundles piled up in the coin case, and a coin transferring mechanism for receiving a row of coin bundles from the coin case by pushing the coin bundles by the coin pushing mechanism and for feeding the coin bundles one by one into a coin accommodating space in response to the discharge of the coin bundles.
    Type: Grant
    Filed: February 26, 1987
    Date of Patent: June 20, 1989
    Assignee: Kabushiki Kaisha Sigma
    Inventors: Shunichi Nakamura, Kouichi Iimura, Kikuo Nakamura, Susumu Ozawa