Patents by Inventor Susumu Sawada

Susumu Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9320155
    Abstract: A ceramic substrate composite includes a conductor pattern composite and an insulating layer on a ceramic substrate. The ceramic substrate composite is formed such that the conductor pattern composite and the insulating layer are provided on the ceramic substrate with each other so that the insulating layer overlaps a part of the conductor pattern composite. The conductor pattern composite is composed of a conductor portion and an insulating portion that exists locally in the conductor portion, and the insulating portion is an insulating material that constitutes the insulating layer.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 19, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Taiji Kuroiwa, Seiichi Nakatani, Yoshihisa Yamashita, Susumu Sawada
  • Patent number: 9236338
    Abstract: A method for manufacturing a build-up substrate, the build-up substrate comprising an insulating layer and a wiring pattern layer stacked over a circuit substrate, said method comprising the steps of: (i) applying a photoactive metal oxide precursor material to one or both sides of the circuit substrate with a wiring pattern, and drying the applied photoactive metal oxide precursor material to form an insulating film; (ii) forming an opening for a via hole in the insulating film by exposure and development of the insulating film; (iii) applying a heat treatment to the insulating film to convert the insulating film into a metal oxide film, thereby forming a build-up insulating layer of the metal oxide film; and (iv) plating the build-up insulating layer to form via holes in the openings, forming a metal layer on the build-up insulating layer, and etching the metal layer to form a build-up wiring pattern; and (v) repeating the steps from (i) to (iv) at least one time.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: January 12, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Seiichi Nakatani, Koji Kawakita, Susumu Sawada, Yoshihisa Yamashita
  • Publication number: 20150364661
    Abstract: An electronic part package comprises a sealing resin layer, an electronic part and a metal plating pattern layer. The sealing resin layer is provided with a principal surface including a first region that has a bellows-like shape having alternate ridges and valleys and a second region that is flat. The electronic part includes an electrode having a principal surface and is covered by the sealing resin layer except the principal surface, which is surrounded by the second region. The metal plating pattern layer is integrally provided on the first and second regions and on the principal surface of the electrode. A portion of the metal plating pattern layer, the portion located on the first region, has a bellows-like shape having alternate ridges and valleys along an outline of the first region.
    Type: Application
    Filed: June 3, 2015
    Publication date: December 17, 2015
    Inventors: SUSUMU SAWADA, YOSHIHIRO TOMITA, KOJI KAWAKITA, MASANORI NOMURA
  • Publication number: 20150280093
    Abstract: There is provided a light-emitting device comprising a light-emitting element, an element electrode, an extending-wiring electrode and a support. In the light-emitting device of the present invention, the light-emitting element is supported and secured by the support in such a form that a principal surface of the support and an active surface of the light-emitting element are approximately flush with each other. Further, the extending-wiring electrode is in a surface contact with the element electrode such that the extending-wiring electrode extends beyond a periphery of the light-emitting element to the principal surface of the support, wholly covering the active surface of the light-emitting element.
    Type: Application
    Filed: August 2, 2013
    Publication date: October 1, 2015
    Inventors: Yoshihiro Tomita, Susumu Sawada, Seiichi Nakatani, Koji Kawakita, Yoshihisa Yamashita
  • Publication number: 20150236233
    Abstract: A method for manufacturing an electronic component package comprises: (i) preparing a metal foil having opposed principal surface “A” for placement of an electronic component and principal surface “B”, and a through-hole located in an electronic component-placement region of the principal surface “A”; (ii) placing the electronic component on the metal foil such that the electronic component is positioned in the electronic component-placement region, and an opening of the through-hole is capped with an electrode of the electronic component; (iii) forming a sealing resin layer on the principal surface “A” such that the electronic component is covered with the sealing resin layer; and (iv) forming a metal plating layer on the principal surface “B”. A dry plating process and a subsequent wet plating process are performed to form the metal plating layer in the (iv) such that the through-hole is filled with the metal plating layer, and the metal foil and the metal plating layer are integrated with each other.
    Type: Application
    Filed: December 20, 2013
    Publication date: August 20, 2015
    Inventors: Yoshihisa Yamashita, Seiichi Nakatani, Koji Kawakita, Susumu Sawada
  • Publication number: 20150228619
    Abstract: There is provided a method for manufacturing an electronic component package, wherein a first electronic component and a second electronic component are placed on a carrier, and a sealing resin layer is formed on the carrier, followed by the carrier being peeled away to be removed, and thereby providing a package precursor in which the first and second electronic components are embedded such that an electrode of at least one of the first and second electronic components is exposed at a surface of the sealing resin layer. Upon the placing of the first and second electronic components, the first and second electronic components are positioned such that their height levels differ from each other. After the removal of the carrier, a metal plating layer is formed such that the metal plating layer is in contact with the exposed surface of the electrode of the at least one of the first and second electronic components.
    Type: Application
    Filed: December 20, 2013
    Publication date: August 13, 2015
    Inventors: Susumu Sawada, Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita
  • Publication number: 20150221842
    Abstract: There is provided a method for manufacturing an electronic component package. The method includes (i) providing a package precursor in which an electronic component is embedded such that an electrode of the electronic component is exposed at a surface of a sealing resin layer; (ii) forming a first metal plating layer such that the first metal plating layer is in contact with the exposed surface of the electrode of the electronic component; (iii) disposing a metal foil in face-to-face spaced relationship with respect to the first metal plating layer; and (iv) forming a second metal plating layer, wherein in the step (iv), the second metal plating layer is formed to fill a clearance between the first metal plating layer and the metal foil with the second metal plating layer, and thereby integrating the metal foil, the first metal plating layer and the second metal plating layer with each other.
    Type: Application
    Filed: December 20, 2013
    Publication date: August 6, 2015
    Applicant: Panasonic Intellectual Property Management Co., Lt
    Inventors: Kazuma Mima, Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita, Susumu Sawada
  • Publication number: 20150214129
    Abstract: There is provided a method for manufacturing an electronic component package, wherein a package precursor is provided, in which an electronic component is embedded in a sealing resin layer such that an electrode of the electronic component is exposed at a surface of the sealing resin layer. In the manufacturing method of the present invention, a combination of a formation process of a plurality of metal plating layers and a patterning process of the metal plating layers is provided to form a step-like metal plating layer, the formation process being performed by sequential dry and wet plating processes with respect to the package precursor, the patterning process being performed by a patterning of at least two of the metal plating layers.
    Type: Application
    Filed: December 20, 2013
    Publication date: July 30, 2015
    Inventors: Koji Kawakita, Seiichi Nakatani, Susumu Sawada, Yoshihisa Yamashita
  • Publication number: 20150155251
    Abstract: There is provided a semiconductor device. The semiconductor device of the present invention includes a semiconductor element and a metal buffer layer in an electrical connection to the semiconductor element. The metal buffer layer and the semiconductor element are in a connection with each other by mutual surface contact of the metal buffer layer and the semiconductor element. The metal buffer layer is an external connection terminal used for a mounting with respect to a secondary mount substrate, and the metal buffer layer serves as a buffer part having a stress-relaxation effect between the semiconductor element and the secondary mount substrate.
    Type: Application
    Filed: August 2, 2013
    Publication date: June 4, 2015
    Inventors: Koji Kawakita, Susumu Sawada, Seiichi Nakatani, Yoshihisa Yamashita
  • Publication number: 20150084080
    Abstract: There is provided a light-emitting device comprising a light-emitting element and a substrate for light-emitting element. The light-emitting element is in a mounted state on a mounting surface of the substrate, the mounting surface being one of two opposed main surfaces of the substrate. The substrate is provided with a protection element for the light-emitting element, the protection element comprising a voltage-dependent resistive layer embedded in the substrate, and comprising a first electrode and a second electrode each of which is in connection with the voltage-dependent resistive layer. The mounted light-emitting element is in an overlapping relation with the voltage-dependent resistive layer. A reflective layer is provided on at least one of the substrate and the voltage-dependent resistive layer such that the reflective layer is located adjacent to the first electrode which is in contact with a substrate exposure surface of the voltage-dependent resistive layer.
    Type: Application
    Filed: February 14, 2013
    Publication date: March 26, 2015
    Inventors: Koji Kawakita, Seiichi Nakatani, Tatsuo Ogawa, Susumu Sawada
  • Publication number: 20150076545
    Abstract: There is provided a method for manufacturing an electronic component package. The method includes the steps: (i) disposing a metal pattern layer on an adhesive carrier; (ii) placing at least one kind of electronic component on the adhesive carrier, the placed electronic component being not overlapped with respect to the metal pattern layer; (iii) forming a sealing resin layer on the adhesive carrier, and thereby producing a precursor of the electronic component package; (iv) peeling off the adhesive carrier of the precursor, whereby the metal pattern layer and an electrode of the electronic component are exposed at the surface of the sealing resin layer; and (v) forming a metal plating layer such that the metal plating layer is in contact with the exposed surface of the metal pattern layer and the exposed surface of the electrode of the electronic component.
    Type: Application
    Filed: August 2, 2013
    Publication date: March 19, 2015
    Applicant: Panasonic Intellectual Property Management Co., Lt
    Inventors: Seiichi Nakatani, Yoshihisa Yamashita, Koji Kawakita, Susumu Sawada
  • Publication number: 20150008467
    Abstract: There is provided a light-emitting device comprising a light-emitting element. The light-emitting device of the present invention comprises an electrode part for the light-emitting element; a reflective layer provided on the electrode part; and the light-emitting element provided on the reflective layer such that the light-emitting element is in contact with at least a part of the reflective layer, wherein the light-emitting element and the electrode part are in an electrical connection with each other by mutual surface contact via the at least a part of the reflective layer, wherein the electrode part serves as a supporting layer for supporting the light-emitting element, and wherein the electrode part extends toward the outside of the light-emitting element and beyond the light-emitting element.
    Type: Application
    Filed: January 28, 2013
    Publication date: January 8, 2015
    Inventors: Susumu Sawada, Seiichi Nakatani, Koji Kawakita, Yoshihisa Yamashita
  • Publication number: 20140131076
    Abstract: In the present invention, a ceramic substrate composite comprising, on a ceramic substrate, a conductor pattern composite and an insulating layer is provided. The ceramic substrate composite of the present invention is characterized in that the conductor pattern composite and the insulating layer are provided on the ceramic substrate with each other so that the insulating layer overlaps a part of the conductor pattern composite; and wherein the conductor pattern composite is composed of a conductor portion and an insulating portion that exists locally in the conductor portion, the insulating portion being an insulating material that constitutes the insulating layer.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 15, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Taiji Kuroiwa, Seiichi Nakatani, Yoshihisa Yamashita, Susumu Sawada
  • Publication number: 20140124777
    Abstract: A method for manufacturing a build-up substrate, the build-up substrate comprising an insulating layer and a wiring pattern layer stacked over a circuit substrate, said method comprising the steps of: (i) applying a photoactive metal oxide precursor material to one or both sides of the circuit substrate with a wiring pattern, and drying the applied photoactive metal oxide precursor material to form an insulating film; (ii) forming an opening for a via hole in the insulating film by exposure and development of the insulating film; (iii) applying a heat treatment to the insulating film to convert the insulating film into a metal oxide film, thereby forming a build-up insulating layer of the metal oxide film; and (iv) plating the build-up insulating layer to form via holes in the openings, forming a metal layer on the build-up insulating layer, and etching the metal layer to form a build-up wiring pattern; and (v) repeating the steps from (i) to (iv) at least one time.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 8, 2014
    Applicant: Panasonic Corporation
    Inventors: Seiichi Nakatani, Koji Kawakita, Susumu Sawada, Yoshihisa Yamashita
  • Patent number: 8501583
    Abstract: A resin containing a conductive particle and a gas bubble generating agent is supplied in a space between the substrates each having a plurality of electrodes. The resin is then heated to melt the conductive particle contained in the resin and generate gas bubbles from the gas bubble generating agent. A step portion is formed on at least one of the substrates. In the process of heating the resin, the resin is pushed aside by the growing gas bubbles, and as a result of that, the conductive particle contained in the resin is led to a space between the electrodes, and a connector is formed in the space. At the same time, the resin is led to a space between parts of the substrates at which the step portion is formed, and cured to fix the distance between the substrates.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: August 6, 2013
    Assignee: Panasonic Corporation
    Inventors: Takashi Kitae, Seiji Karashima, Susumu Sawada, Seiichi Nakatani
  • Patent number: 8297488
    Abstract: A method for forming bumps 19 on electrodes 32 of a wiring board 31 includes the steps of: (a) supplying a fluid 14 containing conductive particles 16 and a gas bubble generating agent onto a first region 17 including the electrodes 32 on the wiring board 31; (b) disposing a substrate 40 having a wall surface 45 formed near the electrodes 32 for forming a meniscus 55 of the fluid 14, so that the substrate 40 faces the wiring board 31; and (c) heating the fluid 14 to generate gas bubbles 30 from the gas bubble generating agent contained in the fluid 14.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: October 30, 2012
    Assignee: Panasonic Corporation
    Inventors: Seiji Karashima, Yasushi Taniguchi, Seiichi Nakatani, Kenichi Hotehama, Takashi Kitae, Susumu Sawada
  • Patent number: 8288778
    Abstract: A semiconductor device having a semiconductor elements formed with higher density is provided. Furthermore an image display device using the semiconductor device is also provided. A semiconductor device comprising a resin film that has a through hole that penetrates from one surface to the other surface thereof, an organic semiconductor disposed inside the through hole, an insulating film on one end of the organic semiconductor, a gate electrode on the insulating film, a source electrode connected electrically to the other end of the organic semiconductor and a drain electrode connected electrically to the other end of the organic semiconductor.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: October 16, 2012
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Susumu Sawada
  • Patent number: 8193526
    Abstract: A semiconductor device having a semiconductor elements formed with higher density is provided. Furthermore an image display device using the semiconductor device is also provided. A semiconductor device comprising a resin film that has a through hole that penetrates from one surface to the other surface thereof, a source electrode disposed along the inner wall of the through hole, a drain electrode disposed along the inner wall of the through hole, a gate electrode disposed on the other surface of the resin film opposing the through hole, an insulating layer disposed on the gate electrode at the bottom of the through hole and an organic semiconductor disposed in the through hole so as to contact the source electrode and the drain electrode, wherein the organic semiconductor makes contact with at least a part of the insulating layer at the bottom of the through hole so that a channel is formed in the organic semiconductor in the vicinity of the insulating layer that is in contact therewith.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: June 5, 2012
    Assignee: Panasonic Corporation
    Inventors: Seiichi Nakatani, Yoshihisa Yamashita, Takashi Kitae, Susumu Sawada
  • Patent number: 8097958
    Abstract: A connection structure (package 10) has a first plate body 101 and a second plate body; in the first plate body 101, a wiring pattern having a plurality of connection terminals 102 is formed, and the second plate body has at least two connection terminals (electrode terminals 104) arranged facing the connection terminals of the first plate body 101. The connection terminals of the first and second plate bodies are connection terminals formed as projections on the surfaces of the first and second plate bodies. A conductive substance 108 is accumulated to cover at least a part of each side face of the connection terminals opposed to each other of the first and second plate bodies, and the connection terminals thus opposed are connected to each other via the conductive substance. The package thus formed is ready for a high-pin-count, narrow-pitch configuration of a next-generation semiconductor chip, and exhibits excellent productivity and reliability.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: January 17, 2012
    Assignee: Panasonic Corporation
    Inventors: Susumu Sawada, Seiichi Nakatani, Seiji Karashima, Takashi Kitae
  • Patent number: 8040200
    Abstract: In a differential transmission line, a substrate has first and second surfaces parallel to each other, and a first grounding conductor is formed on the second surface of the substrate. A dielectric layer is formed on the first grounding conductor, and a second grounding conductor is formed on the dielectric layer. First and the second signal conductors are formed to be parallel to each other on the first surface of the substrate. The first signal conductor and the first and second grounding conductors constitute a first transmission line, and the second signal conductor and the first and second grounding conductors constitute a second transmission line. A slot is formed in the first grounding conductor to three-dimensionally intersect with the first and second signal conductors and to be orthogonal to a longitudinal direction thereof, and a connecting conductor is formed for connecting the first grounding conductor with the second grounding conductor.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 18, 2011
    Assignee: Panasonic Corporation
    Inventors: Akira Minegishi, Toru Yamada, Kazuhide Uriu, Susumu Sawada