Abstract: A semiconductor device includes a memory cell and driver. The memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a floating gate, and a selector gate transistor which has one end of a current path connected to the other end of the current path of the cell transistor and the other end of the current path connected to a source line. The driver is configured to apply, to the control gate of the cell transistor in read, a potential of the same sign as that of a potential applied to the gate of the selector gate transistor.

Abstract: According to an aspect of the embodiment, there is provided a ferroelectric storage device including: a plurality of memory cells repeatedly arranged in a predetermined direction, each memory cell including a ferroelectric film divided for each memory cell; and a word line formed on the ferroelectric film and shared by the plurality of memory cells.

Abstract: A ferroelectric memory device includes a memory cell, read circuit, temperature sensing circuit, and read controller. The memory cell includes a ferroelectric capacitor. The read circuit is configured to read data from the memory cell. The temperature sensing circuit is configured to sense the ambient temperature of the memory cell. The read controller is configured to receive a temperature sensing signal from the temperature sensing circuit, and inhibit a data read operation by the read circuit when the temperature sensed by the temperature sensing circuit is higher than a preset temperature.

Abstract: A semiconductor device includes memory cells and a driver. Each memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a floating gate, and a selector gate transistor which has one end of a current path connected to the other end of the current path of the cell transistor and the other end of the current path connected to a source line. The driver is configured to selectively drive the memory cells, and in read, apply, to a source line connected to a memory cell subjected to read, a potential of a sign opposite to that of a potential applied to the gate of the selector gate transistor in the memory cell to read.

Abstract: A semiconductor device comprising a semiconductor substrate and memory cells. Each memory cell comprises a switching transistor and a ferroelectric capacitor, both formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film held between the lower and upper electrodes. A first wire formed from a deposited wire-material film is connected to the upper electrode of the ferroelectric capacitor. A second wire formed by damascene process is provided on the first wire.

Abstract: A semiconductor device comprises an insulation film that is provided on a semiconductor substrate, a first contact plug that is provided in the insulation film and includes a metal, a first adhesive film that is provided on the insulation film, has a higher oxygen affinity than the metal, and includes an oxide, a second adhesive film that is provided on the first contact plug and has a film thickness that is smaller than a film thickness of the first adhesive film, a first capacitor electrode that is provided on the contact plug and the first adhesive film, has a part in direct contact with the first contact plug, a capacitor insulation film that is provided on the first capacitor electrode, and a second capacitor electrode that is provided on the capacitor insulation film.

Abstract: A semiconductor device comprising a ferroelectric capacitor having improved reliability is disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising a transistor formed on a semiconductor substrate, a ferroelectric capacitor formed above the transistor and comprising a lower electrode, a ferroelectric film and an upper electrode, a first hydrogen barrier film formed over the ferroelectric capacitor, an insulator formed over the first hydrogen barrier film, a contact plug disposed in the insulator and electrically connected with the upper electrode, a second hydrogen barrier film disposed between the contact plug and the insulator continuously, and a wiring connected with the contact plug.

Abstract: A semiconductor device includes a memory cell and driver. The memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a floating gate, and a selector gate transistor which has one end of a current path connected to the other end of the current path of the cell transistor and the other end of the current path connected to a source line. The driver is configured to apply, to the control gate of the cell transistor in read, a potential of the same sign as that of a potential applied to the gate of the selector gate transistor.

Abstract: A semiconductor device includes memory cells and a driver. Each memory cell has a cell transistor which has one end of a current path connected to a bit line and stores data by storing charges in a floating gate, and a selector gate transistor which has one end of a current path connected to the other end of the current path of the cell transistor and the other end of the current path connected to a source line. The driver is configured to selectively drive the memory cells, and in read, apply, to a source line connected to a memory cell subjected to read, a potential of a sign opposite to that of a potential applied to the gate of the selector gate transistor in the memory cell to read.

Abstract: A ferroelectric memory device, which includes a vertical ferroelectric capacitor having an electrode distance smaller than a minimum feature size of lithography technology being used and suitable for the miniaturization, and a method of manufacturing the same are disclosed. According to one aspect of the present invention, it is provided a ferroelectric memory device comprising an MIS transistor formed on a substrate, and a ferroelectric capacitor formed on an interlevel insulator above the MIS transistor, wherein a pair of electrodes of the ferroelectric capacitor are disposed in a channel length direction of the MIS transistor to face each other putting a ferroelectric film in-between, and wherein a distance between the electrodes of the ferroelectric capacitor is smaller than a gate length of the MIS transistor.

Abstract: There is disclosed a ferroelectric memory device comprising an MIS transistor formed on a substrate, a ferroelectric film which is formed above the MIS transistor through an interlayer insulating film, and which has a width substantially equal to a channel length of the MIS transistor, and a same wiring layer which connects a diffusion layer of the MIS transistor formed in a surface region of the substrate to a side surface of the ferroelectric film.

Abstract: A semiconductor storage device comprises a bit line; a word line; a plate line; a ferroelectric capacitor having a ferroelectric substance between electrodes, one of the electrodes being connected to the plate line, the ferroelectric capacitor being capable of storing data; a selection transistor connected between the other of the electrodes of the ferroelectric capacitor and the bit line, the selection transistor being capable of selectively connecting the ferroelectric capacitor to the bit line on the basis of a potential on the word line; a bit line driver corresponding to the bit line to drive the bit line; a word line driver corresponding to the word line to drive the word line; and a plate line driver corresponding to the plate line, the plate line driver including a plurality of plate voltage lines so as to be able to apply a plurality of different voltage values to the plate line, the plate line driver connecting a common single plate voltage line included in the plate voltage lines to the plate line

Abstract: A semiconductor integrated circuit device includes a plurality of memory cells divided into a plurality of groups, and a reference voltage selecting circuit which sets different reference voltages for the respective groups.

Abstract: A semiconductor integrated circuit device includes a plurality of memory cells which have two or more layout patterns and are arranged to make different patterns adjacent to each other, each of the memory cells having a transistor and a ferro-electric capacitor, a plurality of bit lines connected to the memory cells, and a plurality of sense amplifiers each of which is arranged in correspondence with a pair of bit lines connected to the memory cells having the same pattern and uses one of the pair of bit lines as a main input and the other of the pair of bit lines as an input complementary to the main input.

Abstract: A semiconductor device comprises a memory cell array and a source line driver. Each of the memory cells in the memory cell array has a floating gate cell transistor which stores data by accumulating charge in the floating gate and a select gate transistor whose drain is connected to the source of the cell transistor and whose source is connected to a source line. The source line driver is configured so as to drive the source line in a write operation at a potential between the substrate bias potential of the cell transistor and select gate transistor and the ground potential.

Abstract: A semiconductor memory device includes a semiconductor substrate, a transistor formed on the semiconductor substrate, and having a gate electrode and first and second diffusion layers, a first insulating film formed on the transistor, a first multi-layer interconnect layer formed in the first insulating film, and including a plurality of interconnect layers and contacts, a first recessed portion formed to continuously and vertically penetrate the first insulating film including at least two layers of the first multi-layer interconnect layer, and arranged so that at least part of the first recessed portion overlaps with the gate electrode, and a ferroelectric capacitor three-dimensionally formed in the first recessed portion, and having first and second electrodes and a ferroelectric film, the first electrode being electrically connected with the first diffusion layer.

Abstract: A capacitor is configured by a bottom electrode BE, an inter-electrode dielectric D, and a top electrode TE. Directly under the bottom electrode BE, for example, silicon oxide (SiO2) is disposed, and directly above the top electrode TE as well, for example, silicon oxide (SiO2) is disposed. The capacitor is covered with an insulating layer Low-k having a low dielectric constant. The insulating layer Low-k is formed from a material having as low of a dielectric constant as possible in order to reduce the parasitic capacitance between wirings. High-dielectrics High-k for suppressing the swelling of electric lines of force are disposed on side walls of an inter-electrode dielectric D. A dielectric constant of the High-dielectric High-k is at least higher than a dielectric constant of the insulating layer Low-k.

Abstract: A semiconductor integrated circuit device includes a first transistor which has first source and drain and a first gate, a ferro-electric capacitor which is connected to one of the first source and drain, a bit line which is connected to the other of the first source and drain, at least one capacitor connected to the bit line, and a control circuit which electrically connects the capacitor to the bit line or electrically disconnects the capacitor from the bit line.

Abstract: A semiconductor integrated circuit device includes a plurality of memory cells which have two or more layout patterns and are arranged to make different patterns adjacent to each other, each of the memory cells having a transistor and a ferro-electric capacitor, a plurality of bit lines connected to the memory cells, and a plurality of sense amplifiers each of which is arranged in correspondence with a pair of bit lines connected to the memory cells having the same pattern and uses one of the pair of bit lines as a main input and the other of the pair of bit lines as an input complementary to the main input.

Abstract: A semiconductor integrated circuit device includes a first transistor which has first source and drain and a first gate, a ferro-electric capacitor which is connected to one of the first source and drain, a bit line which is connected to the other of the first source and drain, at least one capacitor connected to the bit line, and a control circuit which electrically connects the capacitor to the bit line or electrically disconnects the capacitor from the bit line.