Abstract: Embodiments of the present disclosure relate to a cobalt-boron (CoB) layer for magnetic recording devices, memory devices, and storage devices. In one or more embodiments, the CoB layer is part of a spin-orbit torque (SOT) device. In one or more embodiments, the SOT device is part of an SOT based sensor, an SOT based writer, a memory device (such as a magnetoresistive random-access memory (MRAM) device), and/or a storage device (such as a hard disk drive (HDD) or a tape drive). In one embodiment, an SOT device includes a seed layer, and a cap layer spaced from the seed layer. The SOT device includes a spin-orbit torque (SOT) layer, and a nano layer (NL) between the seed layer and the cap layer. The SOT device includes a cobalt-boron (CoB) layer between the seed layer and the cap layer, and the CoB layer is ferromagnetic.

Abstract: A method of diagnosing deterioration of an exhaust emission control catalyst is provided. The catalyst includes an HC (hydrocarbon) adsorbing part and an oxidation catalyst part. The method includes estimating that an HC discharge amount discharged from the HC adsorbing part is larger than a first value, detecting a parameter relating to a reaction heat of the exhaust emission control catalyst, and diagnosing that the exhaust emission control catalyst is deteriorated when the detected parameter indicates a temperature value lower than a predetermined threshold. The deterioration diagnosis is performed under a first condition that the HC discharge amount is estimated to be larger than the first value.

Abstract: Provided is a thermostat monitor (36) comprising a thermostat open failure detecting part (38) for detecting an open failure of a thermostat when a condition is such that a radiator heat radiation amount (14) radiated from a radiator on a radiator-side cooling water channel is larger than a heater core heat radiation amount (12) radiated from a heater core on a heater core-side cooling water channel, and that a difference between the radiator heat radiation amount and the heater core heat radiation amount is equal to or more than a predetermined value A. Based on a temperature of engine cooling water detected by a temperature sensor positioned in the vicinity of an outlet of an in-engine cooling water channel, it is possible to detect the open failure of the thermostat relatively easily with certainty.

Abstract: Provided is a thermostat monitor (36) comprising a thermostat open failure detecting part (38) for detecting an open failure of a thermostat when a condition is such that a radiator heat radiation amount (14) radiated from a radiator on a radiator-side cooling water channel is larger than a heater core heat radiation amount (12) radiated from a heater core on a heater core-side cooling water channel, and that a difference between the radiator heat radiation amount and the heater core heat radiation amount is equal to or more than a predetermined value A. Based on a temperature of engine cooling water detected by a temperature sensor positioned in the vicinity of an outlet of an in-engine cooling water channel, it is possible to detect the open failure of the thermostat relatively easily with certainty.

Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.

Abstract: A method of diagnosing deterioration of an exhaust emission control catalyst is provided. The catalyst includes an HC (hydrocarbon) adsorbing part and an oxidation catalyst part. The method includes estimating that an HC discharge amount discharged from the HC adsorbing part is larger than a first value, detecting a parameter relating to a reaction heat of the exhaust emission control catalyst, and diagnosing that the exhaust emission control catalyst is deteriorated when the detected parameter indicates a temperature value lower than a predetermined threshold. The deterioration diagnosis is performed under a first condition that the HC discharge amount is estimated to be larger than the first value.

Abstract: A deterioration diagnosing system for an exhaust emission control catalyst of an engine is provided. The catalyst includes an HC adsorbing part and an oxidation catalyst part. The system includes an actual exhaust-emission-control-catalyst temperature parameter detecting module for detecting a parameter correlating with an actual exhaust-emission-control-catalyst temperature. The catalyst also includes a deterioration determining module for receiving a detection value from the actual exhaust-emission-control-catalyst temperature parameter detecting module when predetermined diagnosis executing conditions are met, and determining that the exhaust emission control catalyst is deteriorated when the detection value is smaller than a predetermined diagnostic temperature parameter threshold. The catalyst also includes an HC discharge amount calculating module for calculating an amount of discharging HC from the HC adsorbing part.

Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.

Abstract: A semiconductor memory device includes a memory comprising a plurality of banks; an input section configured to input an address of a bank address, a row address and a column address; and a command generating circuit configured to issue one of a read command, a write command, and a refresh command based on to an input signal. A control section selects a selection bank from the plurality of banks based on the bank address when the read command or the write command is issued from the command generating circuit, performs a read operation or a write operation on the selection bank based on the row address and the column address, and performs a refresh operation on the selection bank when the refresh command is issued immediately after the read command or the write command.

Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.

Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.

Abstract: An exemplary aspect of an embodiment of the present invention is a semiconductor storage device including a power-on reset generator that outputs a first reset signal in accordance with a level of a power supply voltage, a command decoder that moves to a mode set state in accordance with input of an external control pin and outputs mode set information in accordance with a command input from an address pin, an MRS controller that outputs a mode reset signal (MRSPON signal) in accordance with the mode set information, and a reset circuit that outputs a second reset signal initializing each circuit of an operation control section in accordance with the mode reset signal and the first reset signal.

Abstract: A semiconductor memory device includes a memory comprising a plurality of banks; an input section configured to input an address of a bank address, a row address and a column address; and a command generating circuit configured to issue one of a read command, a write command, and a refresh command based on to an input signal. A control section selects a selection bank from the plurality of banks based on the bank address when the read command or the write command is issued from the command generating circuit, performs a read operation or a write operation on the selection bank based on the row address and the column address, and performs a refresh operation on the selection bank when the refresh command is issued immediately after the read command or the write command.

Abstract: A semiconductor memory device includes a control circuit to control an access to a memory cell according to an input command, a transfer mode setting circuit to hold a transfer mode, an address pin input/output with an address in a first transfer mode and input/output with data in a second transfer mode and a switching circuit to switch a connection destination of the address.

Abstract: Disclosed is a logic circuit including first and second input terminals, supplied with respective logic signals, and first and second MOS transistors, having sources respectively connected to associated ones of the first and second input terminals and gates cross-connected to the second and first input terminals. The drains of the first and second MOS transistors are connected in common. The logic circuit also includes a MOS transistor, connected between a first power supply and a common node of the drains of the first and second MOS transistors and having a gate supplied with a reset signal so that the MOS transistor is turned on at the time of resetting. The logic circuit further includes an inverter having an input end connected to the common node.

Abstract: An exemplary aspect of an embodiment of the present invention is a semiconductor storage device including a power-on reset generator that outputs a first reset signal in accordance with a level of a power supply voltage, a command decoder that moves to a mode set state in accordance with input of an external control pin and outputs mode set information in accordance with a command input from an address pin, an MRS controller that outputs a mode reset signal (MRSPON signal) in accordance with the mode set information, and a reset circuit that outputs a second reset signal initializing each circuit of an operation control section in accordance with the mode reset signal and the first reset signal.

Abstract: Disclosed is a semiconductor storage device which has a shared address/data terminal that shares an address terminal and a data terminal. In a latency period extending from receipt of an access command to a cell array to input or output of data, which corresponds to an access command, from the shared address/data terminal, pipeline control is performed in response to receipt of at least one other access command. Input or output of data from the shared address/data terminal corresponding to the other access commands is performed successively following data that corresponds to the initial access command.

Abstract: A semiconductor memory device includes a control circuit to control an access to a memory cell according to an input command, a transfer mode setting circuit to hold a transfer mode, an address pin input/output with an address in a first transfer mode and input/output with data in a second transfer mode and a switching circuit to switch a connection destination of the address.

Abstract: Disclosed is a logic circuit including first and second input terminals, supplied with respective logic signals, and first and second MOS transistors, having sources respectively connected to associated ones of the first and second input terminals and gates cross-connected to the second and first input terminals. The drains of the first and second MOS transistors are connected in common. The logic circuit also includes a MOS transistor, connected between a first power supply and a common node of the drains of the first and second MOS transistors and having a gate supplied with a reset signal so that the MOS transistor is turned on at the time of resetting. The logic circuit further includes an inverter having an input end connected to the common node.

Abstract: Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.